* [dpdk-stable] [PATCH 02/20] net/i40e/base: fix partition id calculation for X722
[not found] <20180925023442.134705-1-qi.z.zhang@intel.com>
@ 2018-09-25 2:34 ` Qi Zhang
2018-09-25 2:34 ` [dpdk-stable] [PATCH 07/20] net/i40e/base: improve the polling mechanism Qi Zhang
` (4 subsequent siblings)
5 siblings, 0 replies; 6+ messages in thread
From: Qi Zhang @ 2018-09-25 2:34 UTC (permalink / raw)
To: beilei.xing; +Cc: dev, ferruh.yigit, helin.zhang, Qi Zhang, stable
This patch overwrites number of ports for X722 devices with support for
OCP PHY mezzanine. The old method with checking if port is disabled in
the PRTGEN_CNF register cannot be used in this case. When the OCP is
removed, ports were seen as disabled, which resulted in wrong calculation
of partition id, that caused WoL to be disabled on certain ports.
Fixes: 3c89193a36fd ("i40e/base: support WOL config for X722")
Cc: stable@dpdk.org
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/i40e/base/i40e_common.c | 23 ++++++++++++++++++++++-
drivers/net/i40e/base/i40e_type.h | 4 +++-
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c
index dce5c3965..ee117bd5e 100644
--- a/drivers/net/i40e/base/i40e_common.c
+++ b/drivers/net/i40e/base/i40e_common.c
@@ -3678,9 +3678,10 @@ STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
u32 valid_functions, num_functions;
u32 number, logical_id, phys_id;
struct i40e_hw_capabilities *p;
+ enum i40e_status_code status;
+ u16 id, ocp_cfg_word0;
u8 major_rev;
u32 i = 0;
- u16 id;
cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
@@ -3972,6 +3973,26 @@ STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
hw->num_ports++;
}
+ /* OCP cards case: if a mezz is removed the ethernet port is at
+ * disabled state in PRTGEN_CNF register. Additional NVM read is
+ * needed in order to check if we are dealing with OCP card.
+ * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
+ * physical ports results in wrong partition id calculation and thus
+ * not supporting WoL.
+ */
+ if (hw->mac.type == I40E_MAC_X722) {
+ if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
+ status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
+ 2 * I40E_SR_OCP_CFG_WORD0,
+ sizeof(ocp_cfg_word0),
+ &ocp_cfg_word0, true, NULL);
+ if (status == I40E_SUCCESS &&
+ (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
+ hw->num_ports = 4;
+ i40e_release_nvm(hw);
+ }
+ }
+
valid_functions = p->valid_functions;
num_functions = 0;
while (valid_functions) {
diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h
index 55acc147e..7dde3bfd2 100644
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -1512,7 +1512,9 @@ struct i40e_hw_port_stats {
#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5)
#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12)
-#define I40E_PTR_TYPE BIT(15)
+#define I40E_PTR_TYPE BIT(15)
+#define I40E_SR_OCP_CFG_WORD0 0x2B
+#define I40E_SR_OCP_ENABLED BIT(15)
/* Shadow RAM related */
#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
--
2.13.6
^ permalink raw reply [flat|nested] 6+ messages in thread* [dpdk-stable] [PATCH 07/20] net/i40e/base: improve the polling mechanism
[not found] <20180925023442.134705-1-qi.z.zhang@intel.com>
2018-09-25 2:34 ` [dpdk-stable] [PATCH 02/20] net/i40e/base: fix partition id calculation for X722 Qi Zhang
@ 2018-09-25 2:34 ` Qi Zhang
2018-09-25 2:34 ` [dpdk-stable] [PATCH 08/20] net/i40e/base: read LLDP config area with correct endianness Qi Zhang
` (3 subsequent siblings)
5 siblings, 0 replies; 6+ messages in thread
From: Qi Zhang @ 2018-09-25 2:34 UTC (permalink / raw)
To: beilei.xing; +Cc: dev, ferruh.yigit, helin.zhang, Qi Zhang, stable
This patch fixes the polling mechanism of GLGEN_RSTAT.DEVSTATE
in the PF Reset path when Global Reset is in progress.
While the driver is polling for the end of the PF Reset and
the Global Reset is triggered, abandon the PF Reset path and
prepare for the upcoming Global Reset.
Cc: stable@dpdk.org
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/i40e/base/i40e_common.c | 35 +++++++++++++++++++++++++++++------
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c
index 18009be3b..0affa98ac 100644
--- a/drivers/net/i40e/base/i40e_common.c
+++ b/drivers/net/i40e/base/i40e_common.c
@@ -1296,6 +1296,29 @@ STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
return media;
}
+/**
+ * i40e_poll_globr - Poll for Global Reset completion
+ * @hw: pointer to the hardware structure
+ * @retry_limit: how many times to retry before failure
+ **/
+STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
+ u32 retry_limit)
+{
+ u32 cnt, reg = 0;
+
+ for (cnt = 0; cnt < retry_limit; cnt++) {
+ reg = rd32(hw, I40E_GLGEN_RSTAT);
+ if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
+ return I40E_SUCCESS;
+ i40e_msec_delay(100);
+ }
+
+ DEBUGOUT("Global reset failed.\n");
+ DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
+
+ return I40E_ERR_RESET_FAILED;
+}
+
#define I40E_PF_RESET_WAIT_COUNT 200
/**
* i40e_pf_reset - Reset the PF
@@ -1365,14 +1388,14 @@ enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
break;
reg2 = rd32(hw, I40E_GLGEN_RSTAT);
- if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
- DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n");
- DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2);
- return I40E_ERR_NOT_READY;
- }
+ if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
+ break;
i40e_msec_delay(1);
}
- if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
+ if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
+ if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
+ return I40E_ERR_RESET_FAILED;
+ } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
DEBUGOUT("PF reset polling failed to complete.\n");
return I40E_ERR_RESET_FAILED;
}
--
2.13.6
^ permalink raw reply [flat|nested] 6+ messages in thread* [dpdk-stable] [PATCH 08/20] net/i40e/base: read LLDP config area with correct endianness
[not found] <20180925023442.134705-1-qi.z.zhang@intel.com>
2018-09-25 2:34 ` [dpdk-stable] [PATCH 02/20] net/i40e/base: fix partition id calculation for X722 Qi Zhang
2018-09-25 2:34 ` [dpdk-stable] [PATCH 07/20] net/i40e/base: improve the polling mechanism Qi Zhang
@ 2018-09-25 2:34 ` Qi Zhang
2018-09-25 2:34 ` [dpdk-stable] [PATCH 09/20] net/i40e/base: properly clean resources Qi Zhang
` (2 subsequent siblings)
5 siblings, 0 replies; 6+ messages in thread
From: Qi Zhang @ 2018-09-25 2:34 UTC (permalink / raw)
To: beilei.xing; +Cc: dev, ferruh.yigit, helin.zhang, Qi Zhang, stable
The NVM is in little endian so when we read from it we need to do
the correct thing for the endianness of the machine.
Cc: stable@dpdk.org
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/i40e/base/i40e_dcb.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_dcb.c b/drivers/net/i40e/base/i40e_dcb.c
index 7cd444bb3..a26f82b3a 100644
--- a/drivers/net/i40e/base/i40e_dcb.c
+++ b/drivers/net/i40e/base/i40e_dcb.c
@@ -1262,18 +1262,20 @@ static enum i40e_status_code _i40e_read_lldp_cfg(struct i40e_hw *hw,
{
u32 address, offset = (2 * word_offset);
enum i40e_status_code ret;
+ __le16 raw_mem;
u16 mem;
ret = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
if (ret != I40E_SUCCESS)
return ret;
- ret = i40e_aq_read_nvm(hw, 0x0, module * 2, sizeof(mem), &mem, true,
- NULL);
+ ret = i40e_aq_read_nvm(hw, 0x0, module * 2, sizeof(raw_mem), &raw_mem,
+ true, NULL);
i40e_release_nvm(hw);
if (ret != I40E_SUCCESS)
return ret;
+ mem = LE16_TO_CPU(raw_mem);
/* Check if this pointer needs to be read in word size or 4K sector
* units.
*/
@@ -1286,12 +1288,13 @@ static enum i40e_status_code _i40e_read_lldp_cfg(struct i40e_hw *hw,
if (ret != I40E_SUCCESS)
goto err_lldp_cfg;
- ret = i40e_aq_read_nvm(hw, module, offset, sizeof(mem), &mem, true,
- NULL);
+ ret = i40e_aq_read_nvm(hw, module, offset, sizeof(raw_mem), &raw_mem,
+ true, NULL);
i40e_release_nvm(hw);
if (ret != I40E_SUCCESS)
return ret;
+ mem = LE16_TO_CPU(raw_mem);
offset = mem + word_offset;
offset *= 2;
--
2.13.6
^ permalink raw reply [flat|nested] 6+ messages in thread* [dpdk-stable] [PATCH 09/20] net/i40e/base: properly clean resources
[not found] <20180925023442.134705-1-qi.z.zhang@intel.com>
` (2 preceding siblings ...)
2018-09-25 2:34 ` [dpdk-stable] [PATCH 08/20] net/i40e/base: read LLDP config area with correct endianness Qi Zhang
@ 2018-09-25 2:34 ` Qi Zhang
2018-09-25 2:34 ` [dpdk-stable] [PATCH 10/20] net/i40e/base: gracefully clean the resources Qi Zhang
2018-09-25 2:34 ` [dpdk-stable] [PATCH 11/20] net/i40e/base: correct global reset timeout calculation Qi Zhang
5 siblings, 0 replies; 6+ messages in thread
From: Qi Zhang @ 2018-09-25 2:34 UTC (permalink / raw)
To: beilei.xing; +Cc: dev, ferruh.yigit, helin.zhang, Qi Zhang, stable
Allocated resources were not freed in the event of a failure in
i40e_init_lan_hmc function. This patch gracefully handles the fail
case after initializing the lan hmc.
Cc: stable@dpdk.org
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/i40e/base/i40e_lan_hmc.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_lan_hmc.c b/drivers/net/i40e/base/i40e_lan_hmc.c
index 510c11826..0afee49b1 100644
--- a/drivers/net/i40e/base/i40e_lan_hmc.c
+++ b/drivers/net/i40e/base/i40e_lan_hmc.c
@@ -114,7 +114,7 @@ enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
DEBUGOUT3("i40e_init_lan_hmc: Tx context: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
txq_num, obj->max_cnt, ret_code);
- goto init_lan_hmc_out;
+ goto free_hmc_out;
}
/* aggregate values into the full LAN object for later */
@@ -137,7 +137,7 @@ enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
DEBUGOUT3("i40e_init_lan_hmc: Rx context: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
rxq_num, obj->max_cnt, ret_code);
- goto init_lan_hmc_out;
+ goto free_hmc_out;
}
/* aggregate values into the full LAN object for later */
@@ -160,7 +160,7 @@ enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
DEBUGOUT3("i40e_init_lan_hmc: FCoE context: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
fcoe_cntx_num, obj->max_cnt, ret_code);
- goto init_lan_hmc_out;
+ goto free_hmc_out;
}
/* aggregate values into the full LAN object for later */
@@ -183,7 +183,7 @@ enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
DEBUGOUT3("i40e_init_lan_hmc: FCoE filter: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
fcoe_filt_num, obj->max_cnt, ret_code);
- goto init_lan_hmc_out;
+ goto free_hmc_out;
}
/* aggregate values into the full LAN object for later */
@@ -204,7 +204,7 @@ enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
(sizeof(struct i40e_hmc_sd_entry) *
hw->hmc.sd_table.sd_cnt));
if (ret_code)
- goto init_lan_hmc_out;
+ goto free_hmc_out;
hw->hmc.sd_table.sd_entry =
(struct i40e_hmc_sd_entry *)hw->hmc.sd_table.addr.va;
}
@@ -213,6 +213,11 @@ enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
init_lan_hmc_out:
return ret_code;
+free_hmc_out:
+ if (hw->hmc.hmc_obj_virt_mem.va)
+ i40e_free_virt_mem(hw, &hw->hmc.hmc_obj_virt_mem);
+
+ return ret_code;
}
/**
--
2.13.6
^ permalink raw reply [flat|nested] 6+ messages in thread* [dpdk-stable] [PATCH 10/20] net/i40e/base: gracefully clean the resources
[not found] <20180925023442.134705-1-qi.z.zhang@intel.com>
` (3 preceding siblings ...)
2018-09-25 2:34 ` [dpdk-stable] [PATCH 09/20] net/i40e/base: properly clean resources Qi Zhang
@ 2018-09-25 2:34 ` Qi Zhang
2018-09-25 2:34 ` [dpdk-stable] [PATCH 11/20] net/i40e/base: correct global reset timeout calculation Qi Zhang
5 siblings, 0 replies; 6+ messages in thread
From: Qi Zhang @ 2018-09-25 2:34 UTC (permalink / raw)
To: beilei.xing; +Cc: dev, ferruh.yigit, helin.zhang, Qi Zhang, stable
Allocated resources were not freed in the event of failure in
i40e_init_asq function. This patch gracefully handles all failures.
Cc: stable@dpdk.org
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/i40e/base/i40e_adminq.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/i40e/base/i40e_adminq.c b/drivers/net/i40e/base/i40e_adminq.c
index 5736e0cb3..bb4c5c61e 100644
--- a/drivers/net/i40e/base/i40e_adminq.c
+++ b/drivers/net/i40e/base/i40e_adminq.c
@@ -97,6 +97,7 @@ enum i40e_status_code i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
**/
void i40e_free_adminq_asq(struct i40e_hw *hw)
{
+ i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
}
@@ -404,7 +405,7 @@ enum i40e_status_code i40e_init_asq(struct i40e_hw *hw)
/* initialize base registers */
ret_code = i40e_config_asq_regs(hw);
if (ret_code != I40E_SUCCESS)
- goto init_adminq_free_rings;
+ goto init_config_regs;
/* success! */
hw->aq.asq.count = hw->aq.num_asq_entries;
@@ -412,6 +413,10 @@ enum i40e_status_code i40e_init_asq(struct i40e_hw *hw)
init_adminq_free_rings:
i40e_free_adminq_asq(hw);
+ return ret_code;
+
+init_config_regs:
+ i40e_free_asq_bufs(hw);
init_adminq_exit:
return ret_code;
--
2.13.6
^ permalink raw reply [flat|nested] 6+ messages in thread* [dpdk-stable] [PATCH 11/20] net/i40e/base: correct global reset timeout calculation
[not found] <20180925023442.134705-1-qi.z.zhang@intel.com>
` (4 preceding siblings ...)
2018-09-25 2:34 ` [dpdk-stable] [PATCH 10/20] net/i40e/base: gracefully clean the resources Qi Zhang
@ 2018-09-25 2:34 ` Qi Zhang
5 siblings, 0 replies; 6+ messages in thread
From: Qi Zhang @ 2018-09-25 2:34 UTC (permalink / raw)
To: beilei.xing; +Cc: dev, ferruh.yigit, helin.zhang, Qi Zhang, stable
The wait time for Global Reset Ready steady state is calculated based on
the GLGEN_RSTCTL.GRSTDEL value. However, current impelementation multiplied
that value by 20 as a workaround for an issue in SOC platforms.
This resulted in the maximum GLGEN_RSTCTL.GRSTDEL timeout of 6.5 seconds
becoming 130 seconds, which is so long that the VMkernel watchdog thinks
the kernel is frozen and triggers a PSOD.
Cc: stable@dpdk.org
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/i40e/base/i40e_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c
index 0affa98ac..0eb369ff6 100644
--- a/drivers/net/i40e/base/i40e_common.c
+++ b/drivers/net/i40e/base/i40e_common.c
@@ -1342,7 +1342,7 @@ enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
- grst_del = grst_del * 20;
+ grst_del = min(grst_del * 20, 160U);
for (cnt = 0; cnt < grst_del; cnt++) {
reg = rd32(hw, I40E_GLGEN_RSTAT);
--
2.13.6
^ permalink raw reply [flat|nested] 6+ messages in thread