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Fri, 2 Nov 2018 21:04:05 +0000 From: Yongseok Koh To: Thomas Monjalon , "bruce.richardson@intel.com" , "ferruh.yigit@intel.com" CC: "dev@dpdk.org" , Shahaf Shuler , "konstantin.ananyev@intel.com" , "anatoly.burakov@intel.com" , Yongseok Koh , "stable@dpdk.org" Thread-Topic: [PATCH v2] build: disable compiler AVX512F support Thread-Index: AQHUcu+WK09O3nLQfUKZoE958YxG+Q== Date: Fri, 2 Nov 2018 21:04:05 +0000 Message-ID: <20181102210348.28148-1-yskoh@mellanox.com> References: <20181023212318.43082-1-yskoh@mellanox.com> In-Reply-To: <20181023212318.43082-1-yskoh@mellanox.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR05CA0061.namprd05.prod.outlook.com (2603:10b6:a03:74::38) To DB3PR0502MB3980.eurprd05.prod.outlook.com (2603:10a6:8:10::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [209.116.155.178] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0502MB4092; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: zMmG1RewDdf/iZ843z3yTpuv4HWr5/l75yuT2ktE059a5UysOCTcSwOy9tQAmIaQZGM+FUu/+IyAsTDRXpqM0kwlDbwgl80Z2YHmI4KKCzGUXzR4KwiBMIYdHgwek3GoydhAY3hr8SHxYXCD3IxZGUW6pZYTNoZWp1ZmrJcX1J49Jl+i50f4PPQQC9/SU8W50LNuTIJfBeUlAKeYuhc+nb6hea//6092LgZZ6/6lfnXujgW3wrJOBMzW96OoNwXOC9NP0Nc1qHYOUY0SB8Frnu9kRyQU2giNYMDOHs0VZz681nPG+4b8Qyl+mfSsKXLiAozCQKIv/ZERDuL9odK8ojXlJkxRs2e7wYVpkbgydIU= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 901755b4-f30f-4634-95d9-08d64106b92b X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Nov 2018 21:04:05.5186 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB4092 Subject: [dpdk-stable] [PATCH v2] build: disable compiler AVX512F support X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Nov 2018 21:04:10 -0000 This is a workaround to prevent a crash, which might be caused by optimization of newer gcc (7.3.0) on Intel Skylake. Bugzilla ID: 97 Cc: stable@dpdk.org Signed-off-by: Yongseok Koh --- v2: * disable the flag only in case of gcc config/x86/meson.build | 5 +++++ mk/rte.cpuflags.mk | 7 +++++++ 2 files changed, 12 insertions(+) diff --git a/config/x86/meson.build b/config/x86/meson.build index 33efb5e547..8ddca0ea9f 100644 --- a/config/x86/meson.build +++ b/config/x86/meson.build @@ -47,6 +47,11 @@ endif if cc.get_define('__AVX512F__', args: march_opt) !=3D '' dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX512F', 1) compile_time_cpuflags +=3D ['RTE_CPUFLAG_AVX512F'] +else +# disable AVX512F support of gcc as a workaround for Bug 97 + if cc.get_id() =3D=3D 'gcc' and cc.has_argument('-mavx512f') + machine_args +=3D '-mno-avx512f' + endif endif =20 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) diff --git a/mk/rte.cpuflags.mk b/mk/rte.cpuflags.mk index 43ed84155b..a8c26fb011 100644 --- a/mk/rte.cpuflags.mk +++ b/mk/rte.cpuflags.mk @@ -68,6 +68,13 @@ endif ifneq ($(filter $(AUTO_CPUFLAGS),__AVX512F__),) ifeq ($(CONFIG_RTE_ENABLE_AVX512),y) CPUFLAGS +=3D AVX512F +else +# disable AVX512F support of gcc as a workaround for Bug 97 +ifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y) + ifeq ($(shell $(CC) --target-help | grep -q mavx512f && echo 1), 1) + MACHINE_CFLAGS +=3D -mno-avx512f + endif +endif endif endif =20 --=20 2.11.0