[dpdk-stable] patch 'eal/ppc: fix global memory barrier' has been queued to LTS release 18.11.2

[Kevin Traynor <ktraynor@redhat.com>]

Hi,

FYI, your patch has been queued to LTS release 18.11.2

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 04/24/19. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Thanks.

Kevin Traynor

---
From 457170828d8a03416e010a71fc4657822b3567cb Mon Sep 17 00:00:00 2001
From: Dekel Peled <dekelp@mellanox.com>
Date: Mon, 18 Mar 2019 14:58:13 +0200
Subject: [PATCH] eal/ppc: fix global memory barrier

[ upstream commit 8015c5593acc3ed490d75c70ff67961b7e278e38 ]

From previous patch description: "to improve performance on PPC64,
use light weight sync instruction instead of sync instruction."

Excerpt from IBM doc [1], section "Memory barrier instructions":
"The second form of the sync instruction is light-weight sync,
or lwsync.
This form is used to control ordering for storage accesses to system
memory only. It does not create a memory barrier for accesses to
device memory."

This patch removes the use of lwsync, so calls to rte_wmb() and
rte_rmb() will provide correct memory barrier to ensure order of
accesses to system memory and device memory.

[1] https://www.ibm.com/developerworks/systems/articles/powerpc.html

Fixes: d23a6bd04d72 ("eal/ppc: fix memory barrier for IBM POWER")

Signed-off-by: Dekel Peled <dekelp@mellanox.com>
---
 lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
index ce38350bd..797381c0f 100644
--- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
@@ -64,9 +64,5 @@ extern "C" {
  * occur before the STORE operations generated after.
  */
-#ifdef RTE_ARCH_64
-#define	rte_wmb() asm volatile("lwsync" : : : "memory")
-#else
 #define	rte_wmb() asm volatile("sync" : : : "memory")
-#endif
 
 /**
@@ -76,9 +72,5 @@ extern "C" {
  * occur before the LOAD operations generated after.
  */
-#ifdef RTE_ARCH_64
-#define	rte_rmb() asm volatile("lwsync" : : : "memory")
-#else
 #define	rte_rmb() asm volatile("sync" : : : "memory")
-#endif
 
 #define rte_smp_mb() rte_mb()
-- 
2.20.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2019-04-16 15:34:27.862297580 +0100
+++ 0060-eal-ppc-fix-global-memory-barrier.patch	2019-04-16 15:34:25.237178685 +0100
@@ -1,8 +1,10 @@
-From 8015c5593acc3ed490d75c70ff67961b7e278e38 Mon Sep 17 00:00:00 2001
+From 457170828d8a03416e010a71fc4657822b3567cb Mon Sep 17 00:00:00 2001
 From: Dekel Peled <dekelp@mellanox.com>
 Date: Mon, 18 Mar 2019 14:58:13 +0200
 Subject: [PATCH] eal/ppc: fix global memory barrier
 
+[ upstream commit 8015c5593acc3ed490d75c70ff67961b7e278e38 ]
+
 From previous patch description: "to improve performance on PPC64,
 use light weight sync instruction instead of sync instruction."
 
@@ -20,7 +22,6 @@
 [1] https://www.ibm.com/developerworks/systems/articles/powerpc.html
 
 Fixes: d23a6bd04d72 ("eal/ppc: fix memory barrier for IBM POWER")
-Cc: stable@dpdk.org
 
 Signed-off-by: Dekel Peled <dekelp@mellanox.com>
 ---