From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id B6CEDA00E6 for ; Tue, 16 Apr 2019 16:39:21 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AED171B4D8; Tue, 16 Apr 2019 16:39:21 +0200 (CEST) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by dpdk.org (Postfix) with ESMTP id 29C9A1B4D8 for ; Tue, 16 Apr 2019 16:39:20 +0200 (CEST) Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8F6463098558; Tue, 16 Apr 2019 14:39:19 +0000 (UTC) Received: from rh.redhat.com (ovpn-117-214.ams2.redhat.com [10.36.117.214]) by smtp.corp.redhat.com (Postfix) with ESMTP id B10F21001E92; Tue, 16 Apr 2019 14:39:18 +0000 (UTC) From: Kevin Traynor To: Dekel Peled Cc: dpdk stable Date: Tue, 16 Apr 2019 15:37:18 +0100 Message-Id: <20190416143719.21601-60-ktraynor@redhat.com> In-Reply-To: <20190416143719.21601-1-ktraynor@redhat.com> References: <20190416143719.21601-1-ktraynor@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.49]); Tue, 16 Apr 2019 14:39:19 +0000 (UTC) Subject: [dpdk-stable] patch 'eal/ppc: fix global memory barrier' has been queued to LTS release 18.11.2 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to LTS release 18.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 04/24/19. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Thanks. Kevin Traynor --- >From 457170828d8a03416e010a71fc4657822b3567cb Mon Sep 17 00:00:00 2001 From: Dekel Peled Date: Mon, 18 Mar 2019 14:58:13 +0200 Subject: [PATCH] eal/ppc: fix global memory barrier [ upstream commit 8015c5593acc3ed490d75c70ff67961b7e278e38 ] >From previous patch description: "to improve performance on PPC64, use light weight sync instruction instead of sync instruction." Excerpt from IBM doc [1], section "Memory barrier instructions": "The second form of the sync instruction is light-weight sync, or lwsync. This form is used to control ordering for storage accesses to system memory only. It does not create a memory barrier for accesses to device memory." This patch removes the use of lwsync, so calls to rte_wmb() and rte_rmb() will provide correct memory barrier to ensure order of accesses to system memory and device memory. [1] https://www.ibm.com/developerworks/systems/articles/powerpc.html Fixes: d23a6bd04d72 ("eal/ppc: fix memory barrier for IBM POWER") Signed-off-by: Dekel Peled --- lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h index ce38350bd..797381c0f 100644 --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h @@ -64,9 +64,5 @@ extern "C" { * occur before the STORE operations generated after. */ -#ifdef RTE_ARCH_64 -#define rte_wmb() asm volatile("lwsync" : : : "memory") -#else #define rte_wmb() asm volatile("sync" : : : "memory") -#endif /** @@ -76,9 +72,5 @@ extern "C" { * occur before the LOAD operations generated after. */ -#ifdef RTE_ARCH_64 -#define rte_rmb() asm volatile("lwsync" : : : "memory") -#else #define rte_rmb() asm volatile("sync" : : : "memory") -#endif #define rte_smp_mb() rte_mb() -- 2.20.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2019-04-16 15:34:27.862297580 +0100 +++ 0060-eal-ppc-fix-global-memory-barrier.patch 2019-04-16 15:34:25.237178685 +0100 @@ -1,8 +1,10 @@ -From 8015c5593acc3ed490d75c70ff67961b7e278e38 Mon Sep 17 00:00:00 2001 +From 457170828d8a03416e010a71fc4657822b3567cb Mon Sep 17 00:00:00 2001 From: Dekel Peled Date: Mon, 18 Mar 2019 14:58:13 +0200 Subject: [PATCH] eal/ppc: fix global memory barrier +[ upstream commit 8015c5593acc3ed490d75c70ff67961b7e278e38 ] + From previous patch description: "to improve performance on PPC64, use light weight sync instruction instead of sync instruction." @@ -20,7 +22,6 @@ [1] https://www.ibm.com/developerworks/systems/articles/powerpc.html Fixes: d23a6bd04d72 ("eal/ppc: fix memory barrier for IBM POWER") -Cc: stable@dpdk.org Signed-off-by: Dekel Peled ---