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Wed, 22 Jan 2020 13:30:26 +0000 Received: from MN2PR18MB2848.namprd18.prod.outlook.com ([fe80::6de0:6ead:9fc:5beb]) by MN2PR18MB2848.namprd18.prod.outlook.com ([fe80::6de0:6ead:9fc:5beb%3]) with mapi id 15.20.2644.028; Wed, 22 Jan 2020 13:30:26 +0000 Received: from outlook.office365.com (115.113.156.2) by PN1PR0101CA0005.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:e::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2644.19 via Frontend Transport; Wed, 22 Jan 2020 13:30:25 +0000 From: Harman Kalra To: Xiao Wang CC: "david.hunt@intel.com" , "dev@dpdk.org" , "stable@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 2/2] l3fwd-power: fix interrupt disable Thread-Index: AQHVz6QkOqWwHDQUfEysjS++jyKrYaf2sNoA Date: Wed, 22 Jan 2020 13:30:26 +0000 Message-ID: <20200122133004.GA45794@outlook.office365.com> References: <20200121030657.39048-1-xiao.w.wang@intel.com> <20200121030657.39048-3-xiao.w.wang@intel.com> In-Reply-To: <20200121030657.39048-3-xiao.w.wang@intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: PN1PR0101CA0005.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:e::15) To MN2PR18MB2848.namprd18.prod.outlook.com (2603:10b6:208:38::19) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [115.113.156.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1c926314-94b2-4486-28f5-08d79f3f3db8 x-ms-traffictypediagnostic: MN2PR18MB2400: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; 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charset="us-ascii" Content-ID: <2A1E5CFA578202468567D3D8B8432899@namprd18.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 1c926314-94b2-4486-28f5-08d79f3f3db8 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Jan 2020 13:30:26.6088 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 0NjS2lAbKwDNLHcEuhNjziuslriuoSEF6++fbO3cOyc+dCMMWgXfqZ3DyU2U+ZG7PsSDhwd9TIQ7NmuOcs1e+Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB2400 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_05:2020-01-16, 2020-01-17 signatures=0 Subject: Re: [dpdk-stable] [dpdk-dev] [PATCH 2/2] l3fwd-power: fix interrupt disable X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" On Mon, Jan 20, 2020 at 10:06:57PM -0500, Xiao Wang wrote: > Since all related queues' interrupts are turned on before epoll, we need > to turn off all the interrupts after wakeup. This patch fixes the issue > of only turning off the interrupted queues. >=20 > Fixes: b736d64787fc ("examples/l3fwd-power: disable Rx interrupt when wak= ing up") > Cc: stable@dpdk.org >=20 > Signed-off-by: Xiao Wang > --- > examples/l3fwd-power/main.c | 13 +++++++------ > 1 file changed, 7 insertions(+), 6 deletions(-) >=20 > diff --git a/examples/l3fwd-power/main.c b/examples/l3fwd-power/main.c > index ffcc7ecf4..e9b2cb5b3 100644 > --- a/examples/l3fwd-power/main.c > +++ b/examples/l3fwd-power/main.c > @@ -880,9 +880,6 @@ sleep_until_rx_interrupt(int num) > port_id =3D ((uintptr_t)data) >> CHAR_BIT; > queue_id =3D ((uintptr_t)data) & > RTE_LEN2MASK(CHAR_BIT, uint8_t); > - rte_spinlock_lock(&(locks[port_id])); > - rte_eth_dev_rx_intr_disable(port_id, queue_id); > - rte_spinlock_unlock(&(locks[port_id])); > RTE_LOG(INFO, L3FWD_POWER, > "lcore %u is waked up from rx interrupt on" > " port %d queue %d\n", > @@ -892,7 +889,7 @@ sleep_until_rx_interrupt(int num) > return 0; > } > =20 > -static void turn_on_intr(struct lcore_conf *qconf) > +static void turn_on_off_intr(struct lcore_conf *qconf, bool on) > { > int i; > struct lcore_rx_queue *rx_queue; > @@ -905,7 +902,10 @@ static void turn_on_intr(struct lcore_conf *qconf) > queue_id =3D rx_queue->queue_id; > =20 > rte_spinlock_lock(&(locks[port_id])); > - rte_eth_dev_rx_intr_enable(port_id, queue_id); > + if (on) > + rte_eth_dev_rx_intr_enable(port_id, queue_id); > + else > + rte_eth_dev_rx_intr_disable(port_id, queue_id); Hi Wang I tested this patch on octeontx2 platform and have some queries regarding the same: Difference what I observed with this patch is, you are disabling interrupts for all the queues handled by the core which woke up but what is the advantage of doing so?=20 I dont see any difference wrt octeontx2, with and without this patch in term of power saving. Can you please explain what I am missing. Thanks Harman > rte_spinlock_unlock(&(locks[port_id])); > } > } > @@ -1340,9 +1340,10 @@ main_loop(__attribute__((unused)) void *dummy) > else { > /* suspend until rx interrupt triggers */ > if (intr_en) { > - turn_on_intr(qconf); > + turn_on_off_intr(qconf, 1); > sleep_until_rx_interrupt( > qconf->n_rx_queue); > + turn_on_off_intr(qconf, 0); > /** > * start receiving packets immediately > */ > --=20 > 2.15.1 >=20