From: Gavin Hu <gavin.hu@arm.com>
To: dev@dpdk.org
Cc: nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net,
rasland@mellanox.com, drc@linux.vnet.ibm.com,
bruce.richardson@intel.com, konstantin.ananyev@intel.com,
matan@mellanox.com, shahafs@mellanox.com,
viacheslavo@mellanox.com, jerinj@marvell.com,
Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com,
phil.yang@arm.com, joyce.kong@arm.com, steve.capper@arm.com,
stable@dpdk.org
Subject: [dpdk-stable] [PATCH RFC v1 5/6] net/mlx5: non-cacheable mapping defaulted for aarch64
Date: Thu, 13 Feb 2020 20:38:53 +0800 [thread overview]
Message-ID: <20200213123854.203566-6-gavin.hu@arm.com> (raw)
In-Reply-To: <20200213123854.203566-1-gavin.hu@arm.com>
aarch64 does not map pci resources to 'write-combine' nor
cacheable. In Linux Kernel arch_can_pci_mmap_wc() equals to 0 on
aarch64[1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
tree/drivers/pci/pci-sysfs.c?h=v5.4#n1204
Fixes: f078ceb6ae93 ("net/mlx5: fix Tx doorbell write memory barrier")
Cc: stable@dpdk.org
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
---
drivers/net/mlx5/mlx5_txq.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index bc13abfe6..144bab4a6 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -319,7 +319,11 @@ txq_uar_ncattr_init(struct mlx5_txq_ctrl *txq_ctrl, size_t page_size)
off_t cmd;
txq_ctrl->txq.db_heu = priv->config.dbnc == MLX5_TXDB_HEURISTIC;
+#ifdef RTE_ARCH_ARM64
+ txq_ctrl->txq.db_nc = 1;
+#else
txq_ctrl->txq.db_nc = 0;
+#endif
/* Check the doorbell register mapping type. */
cmd = txq_ctrl->uar_mmap_offset / page_size;
cmd >>= MLX5_UAR_MMAP_CMD_SHIFT;
--
2.17.1
next prev parent reply other threads:[~2020-02-13 12:44 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200410164127.54229-1-gavin.hu@arm.com>
[not found] ` <20200213123854.203566-1-gavin.hu@arm.com>
2020-02-13 12:38 ` [dpdk-stable] [PATCH RFC v1 1/6] net/mlx5: relax the barrier for UAR write Gavin Hu
2020-02-13 12:38 ` [dpdk-stable] [PATCH RFC v1 2/6] net/mlx5: use cio barrier before the BF WQE Gavin Hu
2020-02-13 12:38 ` [dpdk-stable] [PATCH RFC v1 3/6] net/mlx5: add missing barrier Gavin Hu
2020-02-13 12:38 ` Gavin Hu [this message]
2020-02-13 12:38 ` [dpdk-stable] [PATCH RFC v1 6/6] net/mlx5: relaxed ordering for multi-packet RQ buffer refcnt Gavin Hu
2020-04-10 16:41 ` [dpdk-stable] [PATCH RFC v2 3/7] net/mlx5: relax barrier to order UAR writes on aarch64 Gavin Hu
2020-04-10 16:41 ` [dpdk-stable] [PATCH RFC v2 4/7] net/mlx5: relax barrier for aarch64 Gavin Hu
2020-04-10 16:41 ` [dpdk-stable] [PATCH RFC v2 6/7] net/mlx5: relax ordering for multi-packet RQ buffer refcnt Gavin Hu
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