From: Gavin Hu <gavin.hu@arm.com>
To: dev@dpdk.org
Cc: nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net,
rasland@mellanox.com, drc@linux.vnet.ibm.com,
bruce.richardson@intel.com, konstantin.ananyev@intel.com,
matan@mellanox.com, shahafs@mellanox.com,
viacheslavo@mellanox.com, jerinj@marvell.com,
Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com,
phil.yang@arm.com, joyce.kong@arm.com, steve.capper@arm.com,
stable@dpdk.org
Subject: [dpdk-stable] [PATCH RFC v2 4/7] net/mlx5: relax barrier for aarch64
Date: Sat, 11 Apr 2020 00:41:24 +0800 [thread overview]
Message-ID: <20200410164127.54229-5-gavin.hu@arm.com> (raw)
In-Reply-To: <20200410164127.54229-1-gavin.hu@arm.com>
In-Reply-To: <20200213123854.203566-1-gavin.hu@arm.com>
To ensure the WQE and doorbell record, which reside in the host memory,
are visible to HW before the blue frame, an ordered mlx5_uar_write call
is sufficient, a rte_wmb is overkill for aarch64.
Fixes: 6cb559d67b83 ("net/mlx5: add vectorized Rx/Tx burst for x86")
Cc: stable@dpdk.org
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
---
drivers/net/mlx5/mlx5_rxtx.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
index da5d81350..228e37de5 100644
--- a/drivers/net/mlx5/mlx5_rxtx.h
+++ b/drivers/net/mlx5/mlx5_rxtx.h
@@ -658,8 +658,7 @@ mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
rte_cio_wmb();
*txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
/* Ensure ordering between DB record and BF copy. */
- rte_wmb();
- mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
+ mlx5_uar_write64(*src, dst, txq->uar_lock);
if (cond)
rte_dma_wmb();
}
--
2.17.1
next prev parent reply other threads:[~2020-04-10 16:42 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200410164127.54229-1-gavin.hu@arm.com>
[not found] ` <20200213123854.203566-1-gavin.hu@arm.com>
2020-02-13 12:38 ` [dpdk-stable] [PATCH RFC v1 1/6] net/mlx5: relax the barrier for UAR write Gavin Hu
2020-02-13 12:38 ` [dpdk-stable] [PATCH RFC v1 2/6] net/mlx5: use cio barrier before the BF WQE Gavin Hu
2020-02-13 12:38 ` [dpdk-stable] [PATCH RFC v1 3/6] net/mlx5: add missing barrier Gavin Hu
2020-02-13 12:38 ` [dpdk-stable] [PATCH RFC v1 5/6] net/mlx5: non-cacheable mapping defaulted for aarch64 Gavin Hu
2020-02-13 12:38 ` [dpdk-stable] [PATCH RFC v1 6/6] net/mlx5: relaxed ordering for multi-packet RQ buffer refcnt Gavin Hu
2020-04-10 16:41 ` [dpdk-stable] [PATCH RFC v2 3/7] net/mlx5: relax barrier to order UAR writes on aarch64 Gavin Hu
2020-04-10 16:41 ` Gavin Hu [this message]
2020-04-10 16:41 ` [dpdk-stable] [PATCH RFC v2 6/7] net/mlx5: relax ordering for multi-packet RQ buffer refcnt Gavin Hu
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