From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CC687A0527 for ; Thu, 9 Jul 2020 03:44:39 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AF6131DC19; Thu, 9 Jul 2020 03:44:39 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 7DE131DA7B; Thu, 9 Jul 2020 03:44:36 +0200 (CEST) IronPort-SDR: RN57TjqkJ5k8Ab7w+VxigtK96UEHMeIAVgApImXIUR9C/AT6LtINq/3i2KFV2WvWH8NQ3RTl5s pZ/7UQjwpQZw== X-IronPort-AV: E=McAfee;i="6000,8403,9676"; a="127994425" X-IronPort-AV: E=Sophos;i="5.75,330,1589266800"; d="scan'208";a="127994425" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2020 18:44:35 -0700 IronPort-SDR: 1YPgKhRKzcjE4tNeXX6W8S6HWV6iIAGhf5/zmk2ZT4vs2U1FbgvWr6KZ1OHo8og6D0Xj4TAprJ 5fEoTRaGbvig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,330,1589266800"; d="scan'208";a="283978584" Received: from dpdk-xuting-second.sh.intel.com ([10.67.116.154]) by orsmga006.jf.intel.com with ESMTP; 08 Jul 2020 18:44:33 -0700 From: Ting Xu To: dev@dpdk.org Cc: cristian.dumitrescu@intel.com, Ting Xu , stable@dpdk.org Date: Thu, 9 Jul 2020 09:48:25 +0800 Message-Id: <20200709014825.13690-1-ting.xu@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200616162705.83575-1-ting.xu@intel.com> References: <20200616162705.83575-1-ting.xu@intel.com> Subject: [dpdk-stable] [PATCH v3] lib/table: fix cache alignment issue X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" When create softnic hash table with 16 keys, it failed on 32bit environment because of the structure rte_bucket_4_16 alignment issue. Add __rte_cache_aligned to ensure correct cache align. Fixes: 8aa327214c ("table: hash") Cc: stable@dpdk.org Signed-off-by: Ting Xu --- v2->v3: Rebase v1->v2: Correct patch time --- lib/librte_table/rte_table_hash_key16.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/librte_table/rte_table_hash_key16.c b/lib/librte_table/rte_table_hash_key16.c index 2cca1c924..5e1665c15 100644 --- a/lib/librte_table/rte_table_hash_key16.c +++ b/lib/librte_table/rte_table_hash_key16.c @@ -44,7 +44,7 @@ struct rte_bucket_4_16 { uint64_t key[4][2]; /* Cache line 2 */ - uint8_t data[0]; + uint8_t data[0] __rte_cache_aligned; }; struct rte_table_hash { -- 2.17.1