From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id EB882A04CC for ; Mon, 21 Sep 2020 12:21:00 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B84261D939; Mon, 21 Sep 2020 12:21:00 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 678AF1D711; Mon, 21 Sep 2020 12:20:57 +0200 (CEST) IronPort-SDR: kR00t6ahgSyKXxC/MbDLCuxN30dvFKOUtxYeQz7e4sv1rIkZV+88OipBL8IplQEmVSjsO2LlTv edL5FCu8+o7g== X-IronPort-AV: E=McAfee;i="6000,8403,9750"; a="224487640" X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="224487640" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2020 03:20:54 -0700 IronPort-SDR: 3T6Evl6xhWYNCbw4plCnlBjqfBa5a9ZyVp/+UJOShQHikmEKzNMoRIXUfyIkb8XDkGZJDAWTjO As0RZf+gXpNw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,286,1596524400"; d="scan'208";a="321708776" Received: from unknown (HELO intel.sh.intel.com) ([10.239.255.60]) by orsmga002.jf.intel.com with ESMTP; 21 Sep 2020 03:20:51 -0700 From: Junyu Jiang To: dev@dpdk.org Cc: Jeff Guo , Beilei Xing , Ferruh Yigit , Junyu Jiang , stable@dpdk.org Date: Mon, 21 Sep 2020 09:59:01 +0000 Message-Id: <20200921095901.7089-1-junyux.jiang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200910015426.3140-1-junyux.jiang@intel.com> References: <20200910015426.3140-1-junyux.jiang@intel.com> Subject: [dpdk-stable] [PATCH v3] net/i40e: fix incorrect byte counters X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" This patch fixed the issue that rx/tx bytes statistics counters overflowed on 48 bit limitation by enlarging the limitation. Fixes: 4861cde46116 ("i40e: new poll mode driver") Cc: stable@dpdk.org Signed-off-by: Junyu Jiang --- doc/guides/nics/i40e.rst | 7 +++++++ drivers/net/i40e/i40e_ethdev.c | 32 ++++++++++++++++++++++++++++++++ drivers/net/i40e/i40e_ethdev.h | 9 +++++++++ 3 files changed, 48 insertions(+) diff --git a/doc/guides/nics/i40e.rst b/doc/guides/nics/i40e.rst index b7430f6c4..4baa58be6 100644 --- a/doc/guides/nics/i40e.rst +++ b/doc/guides/nics/i40e.rst @@ -830,3 +830,10 @@ Tx bytes affected by the link status change For firmware versions prior to 6.01 for X710 series and 3.33 for X722 series, the tx_bytes statistics data is affected by the link down event. Each time the link status changes to down, the tx_bytes decreases 110 bytes. + +RX/TX statistics may be incorrect when register overflowed +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The rx_bytes/tx_bytes statistics register is 48 bit length. Although this limitation is enlarged to 64 bit length +on the software side, but there is no way to detect if the overflow occurred more than once. So rx_bytes/tx_bytes +statistics data is correct when statistics are updated at least once between two overflows. diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 563f21d9d..212338ef0 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -3052,6 +3052,19 @@ i40e_dev_link_update(struct rte_eth_dev *dev, return ret; } +static void +i40e_stat_update_48_in_64(uint64_t *new_bytes, + uint64_t *prev_bytes, + bool offset_loaded) +{ + if (offset_loaded) { + if (I40E_RXTX_BYTES_L_48_BIT(*prev_bytes) > *new_bytes) + *new_bytes += (uint64_t)1 << I40E_48_BIT_WIDTH; + *new_bytes += I40E_RXTX_BYTES_H_16_BIT(*prev_bytes); + } + *prev_bytes = *new_bytes; +} + /* Get all the statistics of a VSI */ void i40e_update_vsi_stats(struct i40e_vsi *vsi) @@ -3073,6 +3086,9 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi) i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx), vsi->offset_loaded, &oes->rx_broadcast, &nes->rx_broadcast); + /* enlarge the limitation when rx_bytes overflowed */ + i40e_stat_update_48_in_64(&nes->rx_bytes, &vsi->prev_rx_bytes, + vsi->offset_loaded); /* exclude CRC bytes */ nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + nes->rx_broadcast) * RTE_ETHER_CRC_LEN; @@ -3099,6 +3115,9 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi) /* GLV_TDPC not supported */ i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded, &oes->tx_errors, &nes->tx_errors); + /* enlarge the limitation when tx_bytes overflowed */ + i40e_stat_update_48_in_64(&nes->tx_bytes, &vsi->prev_tx_bytes, + vsi->offset_loaded); vsi->offset_loaded = true; PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************", @@ -3171,6 +3190,13 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) pf->offset_loaded, &pf->internal_stats_offset.tx_broadcast, &pf->internal_stats.tx_broadcast); + /* enlarge the limitation when internal rx/tx bytes overflowed */ + i40e_stat_update_48_in_64(&pf->internal_stats.rx_bytes, + &pf->internal_prev_rx_bytes, + pf->offset_loaded); + i40e_stat_update_48_in_64(&pf->internal_stats.tx_bytes, + &pf->internal_prev_tx_bytes, + pf->offset_loaded); /* exclude CRC size */ pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast + @@ -3194,6 +3220,9 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) I40E_GLPRT_BPRCL(hw->port), pf->offset_loaded, &os->eth.rx_broadcast, &ns->eth.rx_broadcast); + /* enlarge the limitation when rx_bytes overflowed */ + i40e_stat_update_48_in_64(&ns->eth.rx_bytes, &pf->prev_rx_bytes, + pf->offset_loaded); /* Workaround: CRC size should not be included in byte statistics, * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx * packet. @@ -3252,6 +3281,9 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) I40E_GLPRT_BPTCL(hw->port), pf->offset_loaded, &os->eth.tx_broadcast, &ns->eth.tx_broadcast); + /* enlarge the limitation when tx_bytes overflowed */ + i40e_stat_update_48_in_64(&ns->eth.tx_bytes, &pf->prev_tx_bytes, + pf->offset_loaded); ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h index 19f821829..1466998aa 100644 --- a/drivers/net/i40e/i40e_ethdev.h +++ b/drivers/net/i40e/i40e_ethdev.h @@ -282,6 +282,9 @@ struct rte_flow { #define I40E_ETH_OVERHEAD \ (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) +#define I40E_RXTX_BYTES_H_16_BIT(bytes) ((bytes) & ~I40E_48_BIT_MASK) +#define I40E_RXTX_BYTES_L_48_BIT(bytes) ((bytes) & I40E_48_BIT_MASK) + struct i40e_adapter; struct rte_pci_driver; @@ -399,6 +402,8 @@ struct i40e_vsi { uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ uint8_t vlan_filter_on; /* The VLAN filter enabled */ struct i40e_bw_info bw_info; /* VSI bandwidth information */ + uint64_t prev_rx_bytes; + uint64_t prev_tx_bytes; }; struct pool_entry { @@ -1156,6 +1161,10 @@ struct i40e_pf { uint16_t switch_domain_id; struct i40e_vf_msg_cfg vf_msg_cfg; + uint64_t prev_rx_bytes; + uint64_t prev_tx_bytes; + uint64_t internal_prev_rx_bytes; + uint64_t internal_prev_tx_bytes; }; enum pending_msg { -- 2.17.1