From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 196EAA0527 for ; Mon, 9 Nov 2020 19:45:15 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 10D8072E9; Mon, 9 Nov 2020 19:45:14 +0100 (CET) Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by dpdk.org (Postfix) with ESMTP id 4888772E9 for ; Mon, 9 Nov 2020 19:45:11 +0100 (CET) Received: by mail-wr1-f44.google.com with SMTP id j7so2627479wrp.3 for ; Mon, 09 Nov 2020 10:45:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EWVm+ISwlma481Sg+2ZJbKqvQ4SKNgcOLWUeMjY0w4w=; b=EuCdqPIgUCz5F959C0OuDFuzXDNpi1XMY7WY6e/LWYUde3YC7hP2YB5gpDvrB9iZzU pUbHIrIPKmrBu7pJescRiqJJbEPm8LiYBPH0LZFgKnY6WZOs5lvAHXghAyVONSRKwYoC kXJhbrbB7/9x5Oy/XUUgQejhL6h28RRcviy+qXbeobp2rwQMMXJE8U91M9S0h7Jx050s MYwSzPtT3ZEWhaBwziqyKiWrLHUhcfbyaP6RY3+LswnbP/prW1+I71dm5oi8YoT5XuTP A5ZHRLyMrJ9hgDgmmf0TbI4mgNX3Fd9U00RYnYbigGhU1LiQ8Drj1DcH/bVfeahE3nDA r2hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EWVm+ISwlma481Sg+2ZJbKqvQ4SKNgcOLWUeMjY0w4w=; b=QQKAmOqo0P/xcNSy1jI2i6Eju5jV05F5w8pGkipPTGlxQstgz+KSIm2j6MdkQk4SbH yo4gUmCiCoQOfLyhruoTLEl2b1eDIXTf9P04vVe6SRm6J7qdTsi9hRmGJgQBm5e3PnfK 7GZS35nTiYCYOVOWjILUAJFtyPkl81xuaM6INMtCxxb/9ZEHCq6hYX7v4j+8U8yIum/c pJvMKoimkx1yDFA8edtyADxC7lUuGndLNBG7ieCXPjlBxnZUQ7igEMH+A892ZmsDXFan VTvTCegMVhfai0qpBUlrLp+qgq3GPnz9GTnKF0p3iwgGEUOIo+AvC3pEf9HCW5n4fa5D LL3w== X-Gm-Message-State: AOAM530XwPZzjLDqhrslttVKkqYlTaylSyw5m0QBdLV0GTpbjVLRqop9 nzjgJGqkOo9du+eMF2BSNSA= X-Google-Smtp-Source: ABdhPJymVGj79zi3agNpENGzcwGFoS/SXwJhp/mfqQt5Sz78Tc0QTc9/pEm8PR75SAbhJgUzm43HeQ== X-Received: by 2002:adf:f74e:: with SMTP id z14mr19321582wrp.312.1604947510976; Mon, 09 Nov 2020 10:45:10 -0800 (PST) Received: from localhost ([88.98.246.218]) by smtp.gmail.com with ESMTPSA id f7sm15078998wrx.64.2020.11.09.10.45.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2020 10:45:10 -0800 (PST) From: luca.boccassi@gmail.com To: Michal Krawczyk Cc: Ido Segev , Igor Chauskin , Amit Bernstein , dpdk stable Date: Mon, 9 Nov 2020 18:40:57 +0000 Message-Id: <20201109184111.3463090-69-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201109184111.3463090-1-luca.boccassi@gmail.com> References: <20201028104606.3504127-207-luca.boccassi@gmail.com> <20201109184111.3463090-1-luca.boccassi@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-stable] patch 'net/ena/base: align IO CQ allocation to 4K' has been queued to stable release 19.11.6 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 19.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/11/20. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/bluca/dpdk-stable This queued commit can be viewed at: https://github.com/bluca/dpdk-stable/commit/06d1be2a7cfff924dff99278b8ca1a3fbae223ec Thanks. Luca Boccassi --- >From 06d1be2a7cfff924dff99278b8ca1a3fbae223ec Mon Sep 17 00:00:00 2001 From: Michal Krawczyk Date: Fri, 30 Oct 2020 12:31:19 +0100 Subject: [PATCH] net/ena/base: align IO CQ allocation to 4K [ upstream commit 4be6bc7fa13d2ea52a07c8423a09cfda17b5691c ] Latest generation HW requires IO completion queue descriptors to be aligned to a 4K in order to achieve the best performance. Because of that, the new allocation macros were added, which allows driver to allocate the memory with specified alignment. The previous allocation macros are now wrappers around the macros doing the alignment, with the alignment value equal to cacheline size. Fixes: b68309be44c0 ("net/ena/base: update communication layer for the ENAv2") Signed-off-by: Ido Segev Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_com.c | 26 ++++++++++---------- drivers/net/ena/base/ena_com.h | 2 ++ drivers/net/ena/base/ena_plat_dpdk.h | 36 +++++++++++++++++++++------- 3 files changed, 44 insertions(+), 20 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 592909c1be..f8e8f448e3 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -401,19 +401,21 @@ static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; io_cq->bus = ena_dev->bus; - ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev, - size, - io_cq->cdesc_addr.virt_addr, - io_cq->cdesc_addr.phys_addr, - io_cq->cdesc_addr.mem_handle, - ctx->numa_node, - prev_node); + ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(ena_dev->dmadev, + size, + io_cq->cdesc_addr.virt_addr, + io_cq->cdesc_addr.phys_addr, + io_cq->cdesc_addr.mem_handle, + ctx->numa_node, + prev_node, + ENA_CDESC_RING_SIZE_ALIGNMENT); if (!io_cq->cdesc_addr.virt_addr) { - ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, - size, - io_cq->cdesc_addr.virt_addr, - io_cq->cdesc_addr.phys_addr, - io_cq->cdesc_addr.mem_handle); + ENA_MEM_ALLOC_COHERENT_ALIGNED(ena_dev->dmadev, + size, + io_cq->cdesc_addr.virt_addr, + io_cq->cdesc_addr.phys_addr, + io_cq->cdesc_addr.mem_handle, + ENA_CDESC_RING_SIZE_ALIGNMENT); } if (!io_cq->cdesc_addr.virt_addr) { diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index f1593345e8..fed2dec3e4 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -24,6 +24,8 @@ #define ADMIN_CQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_acq_entry)) #define ADMIN_AENQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aenq_entry)) +#define ENA_CDESC_RING_SIZE_ALIGNMENT (1 << 12) /* 4K */ + /*****************************************************************************/ /*****************************************************************************/ /* ENA adaptive interrupt moderation settings */ diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index a8c33dc4d4..9773be09e7 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -169,7 +169,8 @@ do { \ */ extern rte_atomic32_t ena_alloc_cnt; -#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle) \ +#define ENA_MEM_ALLOC_COHERENT_ALIGNED( \ + dmadev, size, virt, phys, handle, alignment) \ do { \ const struct rte_memzone *mz = NULL; \ ENA_TOUCH(dmadev); ENA_TOUCH(handle); \ @@ -178,9 +179,10 @@ extern rte_atomic32_t ena_alloc_cnt; snprintf(z_name, sizeof(z_name), \ "ena_alloc_%d", \ rte_atomic32_add_return(&ena_alloc_cnt, 1)); \ - mz = rte_memzone_reserve(z_name, size, \ + mz = rte_memzone_reserve_aligned(z_name, size, \ SOCKET_ID_ANY, \ - RTE_MEMZONE_IOVA_CONTIG); \ + RTE_MEMZONE_IOVA_CONTIG, \ + alignment); \ handle = mz; \ } \ if (mz == NULL) { \ @@ -192,13 +194,21 @@ extern rte_atomic32_t ena_alloc_cnt; phys = mz->iova; \ } \ } while (0) +#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle) \ + ENA_MEM_ALLOC_COHERENT_ALIGNED( \ + dmadev, \ + size, \ + virt, \ + phys, \ + handle, \ + RTE_CACHE_LINE_SIZE) #define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, handle) \ ({ ENA_TOUCH(size); ENA_TOUCH(phys); \ ENA_TOUCH(dmadev); \ rte_memzone_free(handle); }) -#define ENA_MEM_ALLOC_COHERENT_NODE( \ - dmadev, size, virt, phys, mem_handle, node, dev_node) \ +#define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED( \ + dmadev, size, virt, phys, mem_handle, node, dev_node, alignment) \ do { \ const struct rte_memzone *mz = NULL; \ ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \ @@ -207,8 +217,8 @@ extern rte_atomic32_t ena_alloc_cnt; snprintf(z_name, sizeof(z_name), \ "ena_alloc_%d", \ rte_atomic32_add_return(&ena_alloc_cnt, 1)); \ - mz = rte_memzone_reserve(z_name, size, node, \ - RTE_MEMZONE_IOVA_CONTIG); \ + mz = rte_memzone_reserve_aligned(z_name, size, node, \ + RTE_MEMZONE_IOVA_CONTIG, alignment); \ mem_handle = mz; \ } \ if (mz == NULL) { \ @@ -220,7 +230,17 @@ extern rte_atomic32_t ena_alloc_cnt; phys = mz->iova; \ } \ } while (0) - +#define ENA_MEM_ALLOC_COHERENT_NODE( \ + dmadev, size, virt, phys, mem_handle, node, dev_node) \ + ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED( \ + dmadev, \ + size, \ + virt, \ + phys, \ + mem_handle, \ + node, \ + dev_node, \ + RTE_CACHE_LINE_SIZE) #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) \ do { \ ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \ -- 2.27.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2020-11-09 18:40:13.764285931 +0000 +++ 0069-net-ena-base-align-IO-CQ-allocation-to-4K.patch 2020-11-09 18:40:11.211312527 +0000 @@ -1 +1 @@ -From 4be6bc7fa13d2ea52a07c8423a09cfda17b5691c Mon Sep 17 00:00:00 2001 +From 06d1be2a7cfff924dff99278b8ca1a3fbae223ec Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit 4be6bc7fa13d2ea52a07c8423a09cfda17b5691c ] + @@ -16 +17,0 @@ -Cc: stable@dpdk.org @@ -29 +30 @@ -index 3686ae05c4..aae68721fb 100644 +index 592909c1be..f8e8f448e3 100644 @@ -32 +33 @@ -@@ -413,19 +413,21 @@ static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, +@@ -401,19 +401,21 @@ static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, @@ -67 +68 @@ -index 8eacaeab0e..64d8f247cb 100644 +index f1593345e8..fed2dec3e4 100644 @@ -70 +71 @@ -@@ -23,6 +23,8 @@ +@@ -24,6 +24,8 @@ @@ -80 +81 @@ -index a6782f3732..48c77f0c19 100644 +index a8c33dc4d4..9773be09e7 100644 @@ -83 +84 @@ -@@ -172,7 +172,8 @@ do { \ +@@ -169,7 +169,8 @@ do { \ @@ -93 +94 @@ -@@ -181,9 +182,10 @@ extern rte_atomic32_t ena_alloc_cnt; +@@ -178,9 +179,10 @@ extern rte_atomic32_t ena_alloc_cnt; @@ -106 +107 @@ -@@ -195,13 +197,21 @@ extern rte_atomic32_t ena_alloc_cnt; +@@ -192,13 +194,21 @@ extern rte_atomic32_t ena_alloc_cnt; @@ -130 +131 @@ -@@ -210,8 +220,8 @@ extern rte_atomic32_t ena_alloc_cnt; +@@ -207,8 +217,8 @@ extern rte_atomic32_t ena_alloc_cnt; @@ -141 +142 @@ -@@ -223,7 +233,17 @@ extern rte_atomic32_t ena_alloc_cnt; +@@ -220,7 +230,17 @@ extern rte_atomic32_t ena_alloc_cnt;