From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id AEFA6A04DB for ; Tue, 17 Nov 2020 09:56:45 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 67EBA4C90; Tue, 17 Nov 2020 09:56:44 +0100 (CET) Received: from mail-lf1-f66.google.com (mail-lf1-f66.google.com [209.85.167.66]) by dpdk.org (Postfix) with ESMTP id 916934C90 for ; Tue, 17 Nov 2020 09:56:42 +0100 (CET) Received: by mail-lf1-f66.google.com with SMTP id s30so29051604lfc.4 for ; Tue, 17 Nov 2020 00:56:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nfware-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=shd9+3khV58oXawbmMcvwNkuqwek1B1QzeLCBH4CaCE=; b=xe4vV97/2jGfBsshg0MEpWEFO1SsUomE5ACwSgNjk89DBNFygnfQ498zB6dSN67x4F kpeRhy5CDMhCaTjfjCAwnKWMNn1G9CmGXk0e3BAIHaCCsFJshhtYOYqsSe4KknMGY9OA 2nZ1cVC76Tcol24D/k9g6ZGPpJ7KnEqZlB2YokqTytV2Qqg/ze5GaD2bzZ4VnU/J1BIu gdROuAJt1ki/SZC7BADnnag1IPn2SFX0chsWqB6vW1u6fdi5GhThxR7J8WltWqbixRkh uwKm/waU5/vt8m+a5swNrkJX6iJ+1HPuI7gUGfgsBXqdF/xFdc3KdOj5tjgvK/Qhav2v m8Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=shd9+3khV58oXawbmMcvwNkuqwek1B1QzeLCBH4CaCE=; b=pd1Ap0wa3ttqGjiA4a4FVTSoTh+Aj3JfaK5RPnYitlGF5SE4TS43rV0yhHAqq+SoF7 XsAkYT8gwT1sFyZjQ9IQen/hTAQJhFXnJd4MUV1wmC0XH4BzQ8yIuv8PpnYTBu7A1PNk d8Ff+DOfRsN/7CpfnxR+48xusGjMBx+fMe/hwKI4gk8cd9KlFiuYfBeRkyBEqxGXPkPd sRqBGngXsDQU0quxhY2P+JDjcoz9RV41Co9j31vTZn3LiXFKLBorU4Ry1Ego92PXgrT3 ztW3plFeeqq3ZoUmBPKMi1+8Z4cjLPPQbwithy+s6mwupi5BhCk15Z00uG+cMOYMouOP QTSw== X-Gm-Message-State: AOAM532LCxd6k8iPwIQzR9UIEdHz6FJpf1mpqGq3ra2H+JYJqbD8PzIM X7yQQVnaXCe5kJ4ZBTXDFuFlMA== X-Google-Smtp-Source: ABdhPJxd7L8jGhvJ4k9gqoEvDRQeZvziYAgqRiQB+CEKowUW879q44zUP461x1alEEsa0j/lvWKAyA== X-Received: by 2002:a19:40c7:: with SMTP id n190mr1314125lfa.185.1605603400955; Tue, 17 Nov 2020 00:56:40 -0800 (PST) Received: from localhost.localdomain ([77.105.182.245]) by smtp.gmail.com with ESMTPSA id i66sm3064826lfi.67.2020.11.17.00.56.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Nov 2020 00:56:40 -0800 (PST) From: Igor Ryzhov To: dev@dpdk.org Cc: stable@dpdk.org Date: Tue, 17 Nov 2020 11:56:39 +0300 Message-Id: <20201117085639.40307-1-iryzhov@nfware.com> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-stable] [PATCH] net/i40e: fix counters X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" When low and high registers are read separately, this opens the door to a race condition: - low register is read - NIC updates the registers - high register is read Because of this, we may end up with an incorrect counter value. Let's read the registers in one shot, as it is done in Linux kernel since the introduction of the i40e driver. Fixes: 4861cde46116 ("i40e: new poll mode driver") Cc: stable@dpdk.org Signed-off-by: Igor Ryzhov --- drivers/net/i40e/base/i40e_osdep.h | 10 ++++++++++ drivers/net/i40e/i40e_ethdev.c | 10 +++++++--- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/net/i40e/base/i40e_osdep.h b/drivers/net/i40e/base/i40e_osdep.h index 64b15e1b6138..ebd687240006 100644 --- a/drivers/net/i40e/base/i40e_osdep.h +++ b/drivers/net/i40e/base/i40e_osdep.h @@ -133,6 +133,14 @@ static inline uint32_t i40e_read_addr(volatile void *addr) return rte_le_to_cpu_32(I40E_PCI_REG(addr)); } +#define I40E_PCI_REG64(reg) rte_read64(reg) +#define I40E_PCI_REG64_ADDR(a, reg) \ + ((volatile uint64_t *)((char *)(a)->hw_addr + (reg))) +static inline uint64_t i40e_read64_addr(volatile void *addr) +{ + return rte_le_to_cpu_64(I40E_PCI_REG64(addr)); +} + #define I40E_PCI_REG_WRITE(reg, value) \ rte_write32((rte_cpu_to_le_32(value)), reg) #define I40E_PCI_REG_WRITE_RELAXED(reg, value) \ @@ -145,6 +153,8 @@ static inline uint32_t i40e_read_addr(volatile void *addr) #define I40E_WRITE_REG(hw, reg, value) \ I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), (reg)), (value)) +#define I40E_READ_REG64(hw, reg) i40e_read64_addr(I40E_PCI_REG64_ADDR((hw), (reg))) + #define rd32(a, reg) i40e_read_addr(I40E_PCI_REG_ADDR((a), (reg))) #define wr32(a, reg, value) \ I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((a), (reg)), (value)) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 74f4ac1f9d4e..53b1e9b9e067 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -6451,9 +6451,13 @@ i40e_stat_update_48(struct i40e_hw *hw, { uint64_t new_data; - new_data = (uint64_t)I40E_READ_REG(hw, loreg); - new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) & - I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH; + if (hw->device_id == I40E_DEV_ID_QEMU) { + new_data = (uint64_t)I40E_READ_REG(hw, loreg); + new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) & + I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH; + } else { + new_data = I40E_READ_REG64(hw, loreg); + } if (!offset_loaded) *offset = new_data; -- 2.29.2