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From: Ruifeng Wang <ruifeng.wang@arm.com>
To: Harman Kalra <hkalra@marvell.com>,
	Jerin Jacob <jerin.jacob@caviumnetworks.com>,
	Santosh Shukla <santosh.shukla@caviumnetworks.com>
Cc: dev@dpdk.org, vladimir.medvedkin@intel.com, jerinj@marvell.com,
	hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, nd@arm.com,
	Ruifeng Wang <ruifeng.wang@arm.com>,
	stable@dpdk.org
Subject: [dpdk-stable] [PATCH v2 3/5] net/octeontx: fix build with sve enabled
Date: Fri,  8 Jan 2021 08:25:21 +0000
Message-ID: <20210108082523.1062058-4-ruifeng.wang@arm.com> (raw)
In-Reply-To: <20210108082523.1062058-1-ruifeng.wang@arm.com>

Building with gcc 10.2 with SVE extension enabled got error:

{standard input}: Assembler messages:
{standard input}:91: Error: selected processor does not support `addvl x4,x8,#-1'
{standard input}:95: Error: selected processor does not support `ptrue p1.d,all'
{standard input}:135: Error: selected processor does not support `whilelo p2.d,xzr,x5'
{standard input}:137: Error: selected processor does not support `decb x1'

This is because inline assembly code explicitly resets cpu model to
not have SVE support. Thus SVE instructions generated by compiler
auto vectorization got rejected by assembler.

Fixed the issue by replacing inline assembly with equivalent atomic
built-ins. Compiler will generate LSE instructions for cpu that has
the extension.

Fixes: f0c7bb1bf778 ("net/octeontx/base: add octeontx IO operations")
Cc: jerinj@marvell.com
Cc: stable@dpdk.org

Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
---
 drivers/net/octeontx/base/octeontx_io.h | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/drivers/net/octeontx/base/octeontx_io.h b/drivers/net/octeontx/base/octeontx_io.h
index 04b9ce191..0bf9b100d 100644
--- a/drivers/net/octeontx/base/octeontx_io.h
+++ b/drivers/net/octeontx/base/octeontx_io.h
@@ -58,14 +58,8 @@ do {							\
 static inline uint64_t
 octeontx_reg_ldadd_u64(void *addr, int64_t off)
 {
-	uint64_t old_val;
-
-	__asm__ volatile(
-		" .cpu		generic+lse\n"
-		" ldadd	%1, %0, [%2]\n"
-		: "=r" (old_val) : "r" (off), "r" (addr) : "memory");
-
-	return old_val;
+	return (uint64_t)__atomic_fetch_add((int64_t *)addr, off,
+						__ATOMIC_RELAXED);
 }
 
 /**
@@ -97,10 +91,8 @@ octeontx_reg_lmtst(void *lmtline_va, void *ioreg_va, const uint64_t cmdbuf[],
 		}
 
 		/* LDEOR initiates atomic transfer to I/O device */
-		__asm__ volatile(
-			" .cpu		generic+lse\n"
-			" ldeor	xzr, %0, [%1]\n"
-			: "=r" (result) : "r" (ioreg_va) : "memory");
+		result = __atomic_fetch_xor((uint64_t *)ioreg_va, 0,
+						__ATOMIC_RELAXED);
 	} while (!result);
 }
 
-- 
2.25.1


  parent reply	other threads:[~2021-01-08  8:26 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20201218101210.356836-1-ruifeng.wang@arm.com>
     [not found] ` <20210108082523.1062058-1-ruifeng.wang@arm.com>
2021-01-08  8:25   ` [dpdk-stable] [PATCH v2 2/5] net/hns3: " Ruifeng Wang
2021-01-09  0:06     ` Honnappa Nagarahalli
2021-01-09  2:11       ` oulijun
2021-01-11  2:39         ` Ruifeng Wang
2021-01-11 13:38           ` Honnappa Nagarahalli
2021-01-09  2:15     ` oulijun
2021-01-11  2:27       ` Ruifeng Wang
2021-01-08  8:25   ` Ruifeng Wang [this message]
2021-01-08  8:25   ` [dpdk-stable] [PATCH v2 4/5] common/octeontx2: " Ruifeng Wang
2021-01-08 10:29     ` [dpdk-stable] [EXT] " Pavan Nikhilesh Bhagavatula
2021-01-11  9:51       ` Ruifeng Wang
     [not found] ` <20210112025709.1121523-1-ruifeng.wang@arm.com>
2021-01-12  2:57   ` [dpdk-stable] [PATCH v3 2/5] net/hns3: " Ruifeng Wang
2021-01-13  2:16     ` Honnappa Nagarahalli
2021-01-12  2:57   ` [dpdk-stable] [PATCH v3 3/5] net/octeontx: " Ruifeng Wang
2021-01-12  4:39     ` [dpdk-stable] [dpdk-dev] " Jerin Jacob
2021-01-12  2:57   ` [dpdk-stable] [PATCH v3 4/5] common/octeontx2: " Ruifeng Wang
2021-01-12  4:38     ` [dpdk-stable] [dpdk-dev] " Jerin Jacob

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