From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 71310A04B5 for ; Tue, 12 Jan 2021 03:58:00 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 615EB140D22; Tue, 12 Jan 2021 03:58:00 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id EF7F1140CFC; Tue, 12 Jan 2021 03:57:57 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7754B101E; Mon, 11 Jan 2021 18:57:57 -0800 (PST) Received: from net-arm-n1amp-01.shanghai.arm.com (net-arm-n1amp-01.shanghai.arm.com [10.169.208.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A6CD43F66E; Mon, 11 Jan 2021 18:57:52 -0800 (PST) From: Ruifeng Wang To: "Wei Hu (Xavier)" , "Min Hu (Connor)" , Yisen Zhuang , Lijun Ou , Chengwen Feng , Chengchang Tang , Huisong Li Cc: dev@dpdk.org, vladimir.medvedkin@intel.com, pbhagavatula@marvell.com, jerinj@marvell.com, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, nd@arm.com, Ruifeng Wang , stable@dpdk.org Date: Tue, 12 Jan 2021 02:57:05 +0000 Message-Id: <20210112025709.1121523-3-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210112025709.1121523-1-ruifeng.wang@arm.com> References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210112025709.1121523-1-ruifeng.wang@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [dpdk-stable] [PATCH v3 2/5] net/hns3: fix build with sve enabled X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Building with SVE extension enabled stopped with error: error: ACLE function ‘svwhilelt_b64_s32’ requires ISA extension ‘sve’ 18 | #define PG64_256BIT svwhilelt_b64(0, 4) This is caused by unintentional cflags reset. Fixed the issue by not touching cflags, and using flags defined by compiler. Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") Cc: stable@dpdk.org Signed-off-by: Ruifeng Wang --- v3: Removed extra flag, use compiler flag instead. drivers/net/hns3/hns3_rxtx.c | 4 ++-- drivers/net/hns3/meson.build | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 88d3baba4..5ac36b314 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -10,7 +10,7 @@ #include #include #include -#if defined(RTE_ARCH_ARM64) && defined(CC_SVE_SUPPORT) +#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) #include #endif @@ -2467,7 +2467,7 @@ hns3_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, static bool hns3_check_sve_support(void) { -#if defined(RTE_ARCH_ARM64) && defined(CC_SVE_SUPPORT) +#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) return true; #endif diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build index 45cee34d9..5674d986b 100644 --- a/drivers/net/hns3/meson.build +++ b/drivers/net/hns3/meson.build @@ -32,7 +32,6 @@ deps += ['hash'] if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64') sources += files('hns3_rxtx_vec.c') if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' - cflags = ['-DCC_SVE_SUPPORT'] sources += files('hns3_rxtx_vec_sve.c') endif endif -- 2.25.1