From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2785DA0A06 for ; Wed, 20 Jan 2021 08:08:47 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1A9C2140D41; Wed, 20 Jan 2021 08:08:47 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 9EF1C140D20; Wed, 20 Jan 2021 08:08:44 +0100 (CET) IronPort-SDR: uTqANhcj2pdg2CVjEN3HVjzJCmM3moCRQtDPpScu/xBMVs9LjMEtcVGTOswjyvjQ3wAt6vbY1e GYAk4/eCChpA== X-IronPort-AV: E=McAfee;i="6000,8403,9869"; a="263866812" X-IronPort-AV: E=Sophos;i="5.79,360,1602572400"; d="scan'208";a="263866812" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2021 23:08:40 -0800 IronPort-SDR: TYEIf0C5fTlL0wEroK9z/zfBnqAnmWNJ379Gv6PjPxNtsaTwL4ZrAJ2y5+FKT3jMkelOzWdKfE 3tZg9FHD9EVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,360,1602572400"; d="scan'208";a="426800902" Received: from wuwenjun.sh.intel.com ([10.67.110.153]) by orsmga001.jf.intel.com with ESMTP; 19 Jan 2021 23:08:38 -0800 From: Wenjun Wu To: dev@dpdk.org, jia.guo@intel.com Cc: Wenjun Wu , stable@dpdk.org Date: Wed, 20 Jan 2021 14:53:37 +0800 Message-Id: <20210120065337.230488-1-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-stable] [PATCH v1] net/e1000: fix the invalid flow control mode setting X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" E1000_CTRL register should be updated according to fc_conf->mode's value. Fixes: af75078fece3 ("first public release") Cc: stable@dpdk.org Signed-off-by: Wenjun Wu --- drivers/net/e1000/igb_ethdev.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c index 647aa8d99..a8fc57d2c 100644 --- a/drivers/net/e1000/igb_ethdev.c +++ b/drivers/net/e1000/igb_ethdev.c @@ -3064,6 +3064,7 @@ eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) uint32_t rx_buf_size; uint32_t max_high_water; uint32_t rctl; + uint32_t ctrl; hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); if (fc_conf->autoneg != hw->mac.autoneg) @@ -3101,6 +3102,39 @@ eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) rctl &= ~E1000_RCTL_PMCF; E1000_WRITE_REG(hw, E1000_RCTL, rctl); + + /* + * check if we want to change flow control mode - driver doesn't have native + * capability to do that, so we'll write the registers ourselves + */ + ctrl = E1000_READ_REG(hw, E1000_CTRL); + + /* + * set or clear E1000_CTRL_RFCE and E1000_CTRL_TFCE bits depending + * on configuration + */ + switch (fc_conf->mode) { + case RTE_FC_NONE: + ctrl &= ~E1000_CTRL_RFCE & ~E1000_CTRL_TFCE; + break; + case RTE_FC_RX_PAUSE: + ctrl |= E1000_CTRL_RFCE; + ctrl &= ~E1000_CTRL_TFCE; + break; + case RTE_FC_TX_PAUSE: + ctrl |= E1000_CTRL_TFCE; + ctrl &= ~E1000_CTRL_RFCE; + break; + case RTE_FC_FULL: + ctrl |= E1000_CTRL_RFCE | E1000_CTRL_TFCE; + break; + default: + PMD_INIT_LOG(ERR, "invalid flow control mode"); + return -EINVAL; + } + + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); + E1000_WRITE_FLUSH(hw); return 0; -- 2.25.1