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huawei.com; dkim=none (message not signed) header.d=none;huawei.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT061.mail.protection.outlook.com (10.13.177.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4108.25 via Frontend Transport; Mon, 10 May 2021 16:21:21 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 10 May 2021 16:20:57 +0000 From: Xueming Li To: Chengchang Tang CC: Luca Boccassi , Min Hu , dpdk stable Date: Tue, 11 May 2021 00:02:09 +0800 Message-ID: <20210510160258.30982-180-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210510160258.30982-1-xuemingl@nvidia.com> References: <20210510160258.30982-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b43d764e-b095-476d-0b4a-08d913cfa5f0 X-MS-TrafficTypeDiagnostic: MW3PR12MB4427: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(346002)(136003)(39860400002)(396003)(376002)(36840700001)(46966006)(8936002)(8676002)(478600001)(336012)(6286002)(36756003)(26005)(83380400001)(36860700001)(82310400003)(2906002)(2616005)(426003)(16526019)(54906003)(966005)(186003)(70206006)(6666004)(70586007)(36906005)(7636003)(316002)(7696005)(4326008)(82740400003)(53546011)(356005)(47076005)(6916009)(86362001)(5660300002)(1076003)(55016002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2021 16:21:21.0987 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b43d764e-b095-476d-0b4a-08d913cfa5f0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4427 Subject: [dpdk-stable] patch 'net/hns3: fix queue state when concurrent with reset' has been queued to stable release 20.11.2 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 20.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 05/12/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/33c960aad1e3dac5ea80c656d396871a1e2063b9 Thanks. Xueming Li --- >From 33c960aad1e3dac5ea80c656d396871a1e2063b9 Mon Sep 17 00:00:00 2001 From: Chengchang Tang Date: Sat, 10 Apr 2021 09:11:19 +0800 Subject: [PATCH] net/hns3: fix queue state when concurrent with reset Cc: Luca Boccassi [ upstream commit 18da3c854bb8105818dc23c36eecf3465596052a ] At the end of the reset, the state of queues need to be restored according to the states saved in the driver. If the start and stop operations of the queues are concurrent at this time, it may cause the final status to be uncertain. This patch requires queues to acquire the hw lock before starting and stopping. If the device is being restored due to reset at this time, it will block until the reset is completed. Fixes: fa29fe45a7b4 ("net/hns3: support queue start and stop") Signed-off-by: Chengchang Tang Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_rxtx.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index ba566cdba7..1a554313ba 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -3954,10 +3954,12 @@ hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) if (!hns3_dev_indep_txrx_supported(hw)) return -ENOTSUP; + rte_spinlock_lock(&hw->lock); ret = hns3_reset_queue(hw, rx_queue_id, HNS3_RING_TYPE_RX); if (ret) { hns3_err(hw, "fail to reset Rx queue %u, ret = %d.", rx_queue_id, ret); + rte_spinlock_unlock(&hw->lock); return ret; } @@ -3965,11 +3967,13 @@ hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) if (ret) { hns3_err(hw, "fail to init Rx queue %u, ret = %d.", rx_queue_id, ret); + rte_spinlock_unlock(&hw->lock); return ret; } hns3_enable_rxq(rxq, true); dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; + rte_spinlock_unlock(&hw->lock); return ret; } @@ -3996,12 +4000,14 @@ hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) if (!hns3_dev_indep_txrx_supported(hw)) return -ENOTSUP; + rte_spinlock_lock(&hw->lock); hns3_enable_rxq(rxq, false); hns3_rx_queue_release_mbufs(rxq); hns3_reset_sw_rxq(rxq); dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; + rte_spinlock_unlock(&hw->lock); return 0; } @@ -4016,16 +4022,19 @@ hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) if (!hns3_dev_indep_txrx_supported(hw)) return -ENOTSUP; + rte_spinlock_lock(&hw->lock); ret = hns3_reset_queue(hw, tx_queue_id, HNS3_RING_TYPE_TX); if (ret) { hns3_err(hw, "fail to reset Tx queue %u, ret = %d.", tx_queue_id, ret); + rte_spinlock_unlock(&hw->lock); return ret; } hns3_init_txq(txq); hns3_enable_txq(txq, true); dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; + rte_spinlock_unlock(&hw->lock); return ret; } @@ -4039,6 +4048,7 @@ hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) if (!hns3_dev_indep_txrx_supported(hw)) return -ENOTSUP; + rte_spinlock_lock(&hw->lock); hns3_enable_txq(txq, false); hns3_tx_queue_release_mbufs(txq); /* @@ -4050,6 +4060,7 @@ hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) */ hns3_init_txq(txq); dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; + rte_spinlock_unlock(&hw->lock); return 0; } -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-05-10 23:59:31.235955600 +0800 +++ 0181-net-hns3-fix-queue-state-when-concurrent-with-reset.patch 2021-05-10 23:59:26.620000000 +0800 @@ -1 +1 @@ -From 18da3c854bb8105818dc23c36eecf3465596052a Mon Sep 17 00:00:00 2001 +From 33c960aad1e3dac5ea80c656d396871a1e2063b9 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Luca Boccassi + +[ upstream commit 18da3c854bb8105818dc23c36eecf3465596052a ] @@ -16 +18,0 @@ -Cc: stable@dpdk.org @@ -25 +27 @@ -index 469d8de5df..19adf001a9 100644 +index ba566cdba7..1a554313ba 100644 @@ -28 +30 @@ -@@ -4287,10 +4287,12 @@ hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) +@@ -3954,10 +3954,12 @@ hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) @@ -41 +43 @@ -@@ -4298,11 +4300,13 @@ hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) +@@ -3965,11 +3967,13 @@ hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) @@ -55 +57 @@ -@@ -4329,12 +4333,14 @@ hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) +@@ -3996,12 +4000,14 @@ hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) @@ -70 +72 @@ -@@ -4349,16 +4355,19 @@ hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) +@@ -4016,16 +4022,19 @@ hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) @@ -90 +92 @@ -@@ -4372,6 +4381,7 @@ hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) +@@ -4039,6 +4048,7 @@ hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) @@ -98 +100 @@ -@@ -4383,6 +4393,7 @@ hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) +@@ -4050,6 +4060,7 @@ hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)