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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT026.mail.protection.outlook.com (10.13.177.51) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4108.25 via Frontend Transport; Mon, 10 May 2021 16:05:31 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 10 May 2021 16:05:28 +0000 From: Xueming Li To: Matan Azrad CC: Luca Boccassi , Viacheslav Ovsiienko , dpdk stable Date: Mon, 10 May 2021 23:59:33 +0800 Message-ID: <20210510160258.30982-24-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210510160258.30982-1-xuemingl@nvidia.com> References: <20210510160258.30982-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fb9fc65e-4440-4e0d-1cae-08d913cd6fa7 X-MS-TrafficTypeDiagnostic: MN2PR12MB2992: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(396003)(136003)(39860400002)(376002)(346002)(46966006)(36840700001)(16526019)(4326008)(70586007)(70206006)(55016002)(53546011)(37006003)(2616005)(82740400003)(2906002)(26005)(6636002)(966005)(8936002)(86362001)(1076003)(47076005)(6666004)(7696005)(336012)(54906003)(186003)(316002)(36860700001)(6286002)(7636003)(8676002)(36756003)(5660300002)(82310400003)(426003)(356005)(6862004)(478600001)(36906005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2021 16:05:31.0353 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb9fc65e-4440-4e0d-1cae-08d913cd6fa7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB2992 Subject: [dpdk-stable] patch 'common/mlx5: add DevX command to query WQ' has been queued to stable release 20.11.2 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 20.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 05/12/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/6e06d42907bd796d133b217fc523156b984777cf Thanks. Xueming Li --- >From 6e06d42907bd796d133b217fc523156b984777cf Mon Sep 17 00:00:00 2001 From: Matan Azrad Date: Thu, 25 Feb 2021 10:44:59 +0000 Subject: [PATCH] common/mlx5: add DevX command to query WQ Cc: Luca Boccassi [ upstream commit 542689e92e668c2d734829145996da15de3d0c97 ] Add a DevX command to query Rx queues attributes created by VERBS. Currently support only counter_set_id attribute. This counter ID is managed by the kernel driver and being assigned to any queue created by the kernel. Signed-off-by: Matan Azrad Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 28 ++++++++++++++++++++++++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++ drivers/common/mlx5/mlx5_prm.h | 19 +++++++++++++++++++ drivers/common/mlx5/version.map | 1 + 4 files changed, 51 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 4485a9cd5e..c10be482f3 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -2049,3 +2049,31 @@ mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); return flow_hit_aso_obj; } + +int +mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) +{ +#ifdef HAVE_IBV_FLOW_DV_SUPPORT + uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; + uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; + int rc; + void *rq_ctx; + + MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); + MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); + rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); + if (rc) { + rte_errno = errno; + DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " + "rc = %d, errno = %d.", rc, errno); + return -rc; + }; + rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); + *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); + return 0; +#else + (void)wq; + (void)counter_set_id; + return -ENOTSUP; +#endif +} diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 78202eba9d..3fef39654c 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -502,4 +502,7 @@ __rte_internal struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd); + +__rte_internal +int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 00b425ac85..6638f46ec6 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -851,6 +851,7 @@ enum { MLX5_CMD_OP_MODIFY_SQ = 0X905, MLX5_CMD_OP_CREATE_RQ = 0x908, MLX5_CMD_OP_MODIFY_RQ = 0x909, + MLX5_CMD_OP_QUERY_RQ = 0x90b, MLX5_CMD_OP_CREATE_TIS = 0x912, MLX5_CMD_OP_QUERY_TIS = 0x915, MLX5_CMD_OP_CREATE_RQT = 0x916, @@ -1810,6 +1811,24 @@ struct mlx5_ifc_modify_rq_out_bits { u8 reserved_at_40[0x40]; }; +struct mlx5_ifc_query_rq_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0xc0]; + struct mlx5_ifc_rqc_bits rq_context; +}; + +struct mlx5_ifc_query_rq_in_bits { + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x8]; + u8 rqn[0x18]; + u8 reserved_at_60[0x20]; +}; + struct mlx5_ifc_create_tis_out_bits { u8 status[0x8]; u8 reserved_at_8[0x18]; diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index 17dd11f635..709b2c708e 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -39,6 +39,7 @@ INTERNAL { mlx5_devx_cmd_query_virtio_q_counters; mlx5_devx_cmd_query_virtq; mlx5_devx_cmd_register_read; + mlx5_devx_cmd_wq_query; mlx5_devx_get_out_command_status; mlx5_devx_alloc_uar; -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-05-10 23:59:27.331139500 +0800 +++ 0025-common-mlx5-add-DevX-command-to-query-WQ.patch 2021-05-10 23:59:26.350000000 +0800 @@ -1 +1 @@ -From 542689e92e668c2d734829145996da15de3d0c97 Mon Sep 17 00:00:00 2001 +From 6e06d42907bd796d133b217fc523156b984777cf Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Luca Boccassi + +[ upstream commit 542689e92e668c2d734829145996da15de3d0c97 ] @@ -13,2 +15,0 @@ -Cc: stable@dpdk.org - @@ -25 +26 @@ -index 0185d57036..2dcc1ff551 100644 +index 4485a9cd5e..c10be482f3 100644 @@ -28,2 +29,3 @@ -@@ -2165,3 +2165,31 @@ mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, - return geneve_tlv_opt_obj; +@@ -2049,3 +2049,31 @@ mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) + flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); + return flow_hit_aso_obj; @@ -31 +33 @@ - ++ @@ -59 +60,0 @@ -+ @@ -61 +62 @@ -index 9dcd917c39..f01d5a8802 100644 +index 78202eba9d..3fef39654c 100644 @@ -64 +65,3 @@ -@@ -539,4 +539,7 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, +@@ -502,4 +502,7 @@ __rte_internal + struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, + uint32_t pd); @@ -66,2 +68,0 @@ - __rte_internal - struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); @@ -73 +74 @@ -index de721aa177..f8327158fd 100644 +index 00b425ac85..6638f46ec6 100644 @@ -76 +77 @@ -@@ -911,6 +911,7 @@ enum { +@@ -851,6 +851,7 @@ enum { @@ -84 +85 @@ -@@ -1890,6 +1891,24 @@ struct mlx5_ifc_modify_rq_out_bits { +@@ -1810,6 +1811,24 @@ struct mlx5_ifc_modify_rq_out_bits { @@ -110 +111 @@ -index 244b9c7339..edd6c0e757 100644 +index 17dd11f635..709b2c708e 100644 @@ -113 +114 @@ -@@ -41,6 +41,7 @@ INTERNAL { +@@ -39,6 +39,7 @@ INTERNAL {