From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0D741A0A0C for ; Mon, 17 May 2021 17:19:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EBBAC410F3; Mon, 17 May 2021 17:19:07 +0200 (CEST) Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2057.outbound.protection.outlook.com [40.107.243.57]) by mails.dpdk.org (Postfix) with ESMTP id 2831240041; Mon, 17 May 2021 17:19:05 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TiLNnCzhoUssnrzN4BeqX9uNAOgmLWY8MfoYyAWf/h1yxq2XknvOK7TosB+LBDhZGFDr1agcYmeaUSPMpSxQNSIb+SWVffCehibyL3fOgnoab5Qit/1/69Liz9JgXLXH+5Ms3NsMHTBX6fMZIzpxhD85+6el6rhP4oa1ULUvzEHxbS3wg5LsIbpomhQiCik++WMqShFqgfGzOtJEnfR1K6rqx2Vru+KlMIQHi9WHP+EFgFUrz8rd685ESmFec10LpdOmOxfSvtnnvQ4RB0ZCoRHvdG5QfUMoeKypC8MCw4xyRdeB1lCAVx9C+Iu1JZrTHf/G+kYw9OKIWIL6JZPw7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=00LZPZJDaMTdmUBbqAH4+6pWMic9EVjTwp50J9hpS1s=; b=nL8HLAN7pZlQLmKaEE5nfmk/QfKcfpxAtTh1gjFBmiaL+0mjq1jUTzd5Tqg/pu5Xq7KBOQjnF0PDfYSoosqiRopYbdT9ZJkWjk59Yw8Jxlqd85muxBU78lbV1MSroM9oFI6VD3gxLQsdYNPvO1L5aFjlJUypcnUQJHXnKYB+pnLMY15iB4gumOCACxkR0IRYhgVXKWiWWpL0MW+OsJbzf+R6TBbWE8cGYfGJe+F6sXnCHriACiQjWmefR+5QoXGcZyqedViffWzieq9RW1Xi9IU3FUxqDxHhzzLOdKb5oRKGifIdrVAdJjTEavny+1s2VWX5d164HoPxjzMt8xWrgA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=00LZPZJDaMTdmUBbqAH4+6pWMic9EVjTwp50J9hpS1s=; b=SNpmfbL7PlEfvWKk8UgQmTxApsbCVt0IQAOrgNmN2ZfmHQI8V7B71OMp+U9CLztn/2UQke/Kb7bfGx9M+U7loaVR1TmBgh01qqqgfyW2pGzPhhu72w5UlRAUCz/Tm7jrGdsOL1OAVLb5eyI8mS5OMv8J1TfI/hlQ7I6XPegbbm5s+F/nHY0P/FhX68dQBZCF8Out1qo2/jy50gz8UNcZqJhz85KpeAA/ltCOUGQScHh4Mqr0bxDXqut7ldfu0BEibNgjzAnVzaV3LDm9liKDGtlu37X6GVfwh/6p2zFaL6eDv38n+M/5FuNpsbR9mXQLnGXvPtJRIiH0wEgxwCY9Mw== Received: from DM5PR2201CA0001.namprd22.prod.outlook.com (2603:10b6:4:14::11) by BY5PR12MB4965.namprd12.prod.outlook.com (2603:10b6:a03:1c4::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.26; Mon, 17 May 2021 15:19:03 +0000 Received: from DM6NAM11FT005.eop-nam11.prod.protection.outlook.com (2603:10b6:4:14:cafe::90) by DM5PR2201CA0001.outlook.office365.com (2603:10b6:4:14::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.25 via Frontend Transport; Mon, 17 May 2021 15:19:03 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT005.mail.protection.outlook.com (10.13.172.238) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4129.25 via Frontend Transport; Mon, 17 May 2021 15:19:02 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 17 May 2021 15:19:00 +0000 From: Bing Zhao To: , , CC: , , , , Date: Mon, 17 May 2021 18:18:41 +0300 Message-ID: <20210517151841.57847-1-bingz@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210512143607.3982046-1-bingz@nvidia.com> References: <20210512143607.3982046-1-bingz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5eb33857-bf96-4bc5-e09b-08d919471a87 X-MS-TrafficTypeDiagnostic: BY5PR12MB4965: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mKso2TXJb3DCMtYPuDRVyd5ERmE1CNUXyBW3erHZ6NUCWUqBQBVVIEdAddGP2emXHWzwlUo8zkck87aIZcCUnfesJraDObClA5mF5puvgFgkPOcHIstE+qB8gF4lE5AmiWBeGvM5jTZ13WXqz0NOC6SyN+6ue6DXX+wWSYajY/6hjQfKZFVYRgPYHH/n+2EAGHc1xMwyYFDwNxqXIbJ5CT+BCAcX3y/GOOg9ch9yE1S6cO8/lZ3ZkK5bhxTM3vFZ39s+nPOp9GUuQuO0OdcDg5A+WnUhbuPaADl0GdrrumIJJ7nMZkgYhs6+dVdEkOxvq5ZivijkYQ7i8eehlWuFBeifyWn+06Ls2hd3sI5PF/eO5RetzHr2GKAGOKFJvUiMn1kj4F06qs+gGVJeZBIwiUylasDzkxeSiiqRiE+4gu6Wdu7r0uL3/BQvDGt5ZmZfq+jTQYH7EtyYy+J3nO12rHkAU3AyMjpH+f6pG0QclmrEeH8H88bj+qpwXlAOPge/PL3BA7wa+d/ORTH9fCamo9PWQFr6/4N+7LZa9tuoq3eBUG4/qaIAyXTYUX139EKK77DBVG+TO8ZOdfJS8HaChOPNwaYmOcPs72EpKZlFikiSSdmyp1aTGbO+vRB+eFgg6iRDKpQcEqP8Xl08Mvhdq40Vs8co5IzRnnW3J1eiuxk= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(39860400002)(396003)(346002)(376002)(36840700001)(46966006)(110136005)(6286002)(107886003)(26005)(4326008)(478600001)(47076005)(336012)(55016002)(54906003)(316002)(36906005)(356005)(186003)(8936002)(426003)(82740400003)(86362001)(2616005)(7696005)(7636003)(8676002)(16526019)(6666004)(36860700001)(82310400003)(2906002)(5660300002)(83380400001)(36756003)(70586007)(1076003)(70206006); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2021 15:19:02.6561 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5eb33857-bf96-4bc5-e09b-08d919471a87 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4965 Subject: [dpdk-stable] [PATCH v3] net/mlx5: fix loopback for DV queue X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" In the past, all the queues and other hardware objects were created through Verbs interface. Currently, most of the objects creation are migrated to Devx interface by default, including queues. Only when the DV is disabled by device arg or eswitch is enabled, all or some of the objects are created through Verbs interface. When using Devx interface to create queues, the kernel driver behavior is different from the case using Verbs. The Tx loopback cannot work properly even if the Tx and Rx queues are configured with loopback attribute. To fix the support self loopback for Tx, a Verbs dummy queue pair needs to be created to trigger the kernel to enable the global loopback capability. This is only required when TIR is created for Rx and loopback is needed. Only CQ and QP are needed for this case, no WQ(RQ) needs to be created. This requirement comes from bugzilla 645, more details can be found in the bugzilla link. Bugzilla ID: 645 Fixes: 6deb19e1b2d2 ("net/mlx5: separate Rx queue object creations") Cc: stable@dpdk.org Signed-off-by: Bing Zhao Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/linux/mlx5_os.c | 5 +- drivers/net/mlx5/linux/mlx5_verbs.c | 121 ++++++++++++++++++++++++++++ drivers/net/mlx5/linux/mlx5_verbs.h | 2 + drivers/net/mlx5/mlx5.h | 11 +++ drivers/net/mlx5/mlx5_devx.c | 2 + drivers/net/mlx5/mlx5_trigger.c | 10 +++ 6 files changed, 150 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index ef7ccba5de..534a56a555 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1632,7 +1632,10 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new; priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release; mlx5_queue_counter_id_prepare(eth_dev); - + priv->obj_ops.lb_dummy_queue_create = + mlx5_rxq_ibv_obj_dummy_lb_create; + priv->obj_ops.lb_dummy_queue_release = + mlx5_rxq_ibv_obj_dummy_lb_release; } else { priv->obj_ops = ibv_obj_ops; } diff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c index 0b0759f33f..d4fa202ac4 100644 --- a/drivers/net/mlx5/linux/mlx5_verbs.c +++ b/drivers/net/mlx5/linux/mlx5_verbs.c @@ -1055,6 +1055,125 @@ mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx) return -rte_errno; } +/* + * Create the dummy QP with minimal resources for loopback. + * + * @param dev + * Pointer to Ethernet device. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_rxq_ibv_obj_dummy_lb_create(struct rte_eth_dev *dev) +{ +#if defined(HAVE_IBV_DEVICE_TUNNEL_SUPPORT) && defined(HAVE_IBV_FLOW_DV_SUPPORT) + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_dev_ctx_shared *sh = priv->sh; + struct ibv_context *ctx = sh->ctx; + struct mlx5dv_qp_init_attr qp_init_attr = {0}; + struct { + struct ibv_cq_init_attr_ex ibv; + struct mlx5dv_cq_init_attr mlx5; + } cq_attr = {{0}}; + + if (dev->data->dev_conf.lpbk_mode) { + /* Allow packet sent from NIC loop back w/o source MAC check. */ + qp_init_attr.comp_mask |= + MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS; + qp_init_attr.create_flags |= + MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC; + } else { + return 0; + } + /* Only need to check refcnt, 0 after "sh" is allocated. */ + if (!!(__atomic_fetch_add(&sh->self_lb.refcnt, 1, __ATOMIC_RELAXED))) { + MLX5_ASSERT(sh->self_lb.ibv_cq && sh->self_lb.qp); + priv->lb_used = 1; + return 0; + } + cq_attr.ibv = (struct ibv_cq_init_attr_ex){ + .cqe = 1, + .channel = NULL, + .comp_mask = 0, + }; + cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){ + .comp_mask = 0, + }; + /* Only CQ is needed, no WQ(RQ) is required in this case. */ + sh->self_lb.ibv_cq = mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(ctx, + &cq_attr.ibv, + &cq_attr.mlx5)); + if (!sh->self_lb.ibv_cq) { + DRV_LOG(ERR, "Port %u cannot allocate CQ for loopback.", + dev->data->port_id); + rte_errno = errno; + goto error; + } + sh->self_lb.qp = mlx5_glue->dv_create_qp(ctx, + &(struct ibv_qp_init_attr_ex){ + .qp_type = IBV_QPT_RAW_PACKET, + .comp_mask = IBV_QP_INIT_ATTR_PD, + .pd = sh->pd, + .send_cq = sh->self_lb.ibv_cq, + .recv_cq = sh->self_lb.ibv_cq, + .cap.max_recv_wr = 1, + }, + &qp_init_attr); + if (!sh->self_lb.qp) { + DRV_LOG(DEBUG, "Port %u cannot allocate QP for loopback.", + dev->data->port_id); + rte_errno = errno; + goto error; + } + priv->lb_used = 1; + return 0; +error: + if (sh->self_lb.ibv_cq) { + claim_zero(mlx5_glue->destroy_cq(sh->self_lb.ibv_cq)); + sh->self_lb.ibv_cq = NULL; + } + (void)__atomic_sub_fetch(&sh->self_lb.refcnt, 1, __ATOMIC_RELAXED); + return -rte_errno; +#else + RTE_SET_USED(dev); + return 0; +#endif +} + +/* + * Release the dummy queue resources for loopback. + * + * @param dev + * Pointer to Ethernet device. + */ +void +mlx5_rxq_ibv_obj_dummy_lb_release(struct rte_eth_dev *dev) +{ +#if defined(HAVE_IBV_DEVICE_TUNNEL_SUPPORT) && defined(HAVE_IBV_FLOW_DV_SUPPORT) + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_dev_ctx_shared *sh = priv->sh; + + if (!priv->lb_used) + return; + MLX5_ASSERT(__atomic_load_n(&sh->self_lb.refcnt, __ATOMIC_RELAXED)); + if (!(__atomic_sub_fetch(&sh->self_lb.refcnt, 1, __ATOMIC_RELAXED))) { + if (sh->self_lb.qp) { + claim_zero(mlx5_glue->destroy_qp(sh->self_lb.qp)); + sh->self_lb.qp = NULL; + } + if (sh->self_lb.ibv_cq) { + claim_zero(mlx5_glue->destroy_cq(sh->self_lb.ibv_cq)); + sh->self_lb.ibv_cq = NULL; + } + } + priv->lb_used = 0; +#else + RTE_SET_USED(dev); + return; +#endif +} + /** * Release an Tx verbs queue object. * @@ -1084,4 +1203,6 @@ struct mlx5_obj_ops ibv_obj_ops = { .txq_obj_new = mlx5_txq_ibv_obj_new, .txq_obj_modify = mlx5_ibv_modify_qp, .txq_obj_release = mlx5_txq_ibv_obj_release, + .lb_dummy_queue_create = NULL, + .lb_dummy_queue_release = NULL, }; diff --git a/drivers/net/mlx5/linux/mlx5_verbs.h b/drivers/net/mlx5/linux/mlx5_verbs.h index 76a79bf4f4..f7e8e2fe98 100644 --- a/drivers/net/mlx5/linux/mlx5_verbs.h +++ b/drivers/net/mlx5/linux/mlx5_verbs.h @@ -9,6 +9,8 @@ int mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx); void mlx5_txq_ibv_obj_release(struct mlx5_txq_obj *txq_obj); +int mlx5_rxq_ibv_obj_dummy_lb_create(struct rte_eth_dev *dev); +void mlx5_rxq_ibv_obj_dummy_lb_release(struct rte_eth_dev *dev); /* Verbs ops struct */ extern const struct mlx5_mr_ops mlx5_mr_verbs_ops; diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index b8a29dd369..32b2817bf2 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -287,6 +287,13 @@ struct mlx5_drop { struct mlx5_rxq_obj *rxq; /* Rx queue object. */ }; +/* Loopback dummy queue resources required due to Verbs API. */ +struct mlx5_lb_ctx { + struct ibv_qp *qp; /* QP object. */ + void *ibv_cq; /* Completion queue. */ + uint16_t refcnt; /* Reference count for representors. */ +}; + #define MLX5_COUNTERS_PER_POOL 512 #define MLX5_MAX_PENDING_QUERIES 4 #define MLX5_CNT_CONTAINER_RESIZE 64 @@ -1128,6 +1135,7 @@ struct mlx5_dev_ctx_shared { /* Meter management structure. */ struct mlx5_aso_ct_pools_mng *ct_mng; /* Management data for ASO connection tracking. */ + struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */ struct mlx5_dev_shared_port port[]; /* per device port data array. */ }; @@ -1287,6 +1295,8 @@ struct mlx5_obj_ops { int (*txq_obj_modify)(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type, uint8_t dev_port); void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); + int (*lb_dummy_queue_create)(struct rte_eth_dev *dev); + void (*lb_dummy_queue_release)(struct rte_eth_dev *dev); }; #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields) @@ -1316,6 +1326,7 @@ struct mlx5_priv { unsigned int sampler_en:1; /* Whether support sampler. */ unsigned int mtr_en:1; /* Whether support meter. */ unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ + unsigned int lb_used:1; /* Loopback queue is referred to. */ uint16_t domain_id; /* Switch domain identifier. */ uint16_t vport_id; /* Associated VF vport index (if any). */ uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 531a81d7fa..78b88f99b4 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -1188,4 +1188,6 @@ struct mlx5_obj_ops devx_obj_ops = { .txq_obj_new = mlx5_txq_devx_obj_new, .txq_obj_modify = mlx5_devx_modify_sq, .txq_obj_release = mlx5_txq_devx_obj_release, + .lb_dummy_queue_create = NULL, + .lb_dummy_queue_release = NULL, }; diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index 879d3171e9..ae7fcca229 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -1068,6 +1068,12 @@ mlx5_dev_start(struct rte_eth_dev *dev) dev->data->port_id, strerror(rte_errno)); goto error; } + if ((priv->config.devx && priv->config.dv_flow_en && + priv->config.dest_tir) && priv->obj_ops.lb_dummy_queue_create) { + ret = priv->obj_ops.lb_dummy_queue_create(dev); + if (ret) + goto error; + } ret = mlx5_txq_start(dev); if (ret) { DRV_LOG(ERR, "port %u Tx queue allocation failed: %s", @@ -1148,6 +1154,8 @@ mlx5_dev_start(struct rte_eth_dev *dev) mlx5_traffic_disable(dev); mlx5_txq_stop(dev); mlx5_rxq_stop(dev); + if (priv->obj_ops.lb_dummy_queue_release) + priv->obj_ops.lb_dummy_queue_release(dev); mlx5_txpp_stop(dev); /* Stop last. */ rte_errno = ret; /* Restore rte_errno. */ return -rte_errno; @@ -1186,6 +1194,8 @@ mlx5_dev_stop(struct rte_eth_dev *dev) priv->sh->port[priv->dev_port - 1].devx_ih_port_id = RTE_MAX_ETHPORTS; mlx5_txq_stop(dev); mlx5_rxq_stop(dev); + if (priv->obj_ops.lb_dummy_queue_release) + priv->obj_ops.lb_dummy_queue_release(dev); mlx5_txpp_stop(dev); return 0; -- 2.27.0