From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BCE5CA0548 for ; Mon, 17 May 2021 21:18:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8693E40041; Mon, 17 May 2021 21:18:04 +0200 (CEST) Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) by mails.dpdk.org (Postfix) with ESMTP id 100A040041 for ; Mon, 17 May 2021 21:18:03 +0200 (CEST) Received: by mail-pf1-f171.google.com with SMTP id b13so1904961pfv.4 for ; Mon, 17 May 2021 12:18:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=vKtLm5pc4stTyYZ1Hcchkb1u7lTK9pqf/yKNaClXVcU=; b=aIs3ZVsAIx3ONaWIRiOTrwww3dmempyerow0gYIMO4mfZb8IFcVdmRkJINw+uFgz7E j/RRbMtIz9aOcsd9Vz9llWkn04q1MGZHJSjwBswiCTSJv3KlVT89mATU2mu0yEHnQM2M liTTi9UtnpPveEnhS2lXKgk7c3W94MX+GAiDA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=vKtLm5pc4stTyYZ1Hcchkb1u7lTK9pqf/yKNaClXVcU=; b=ZLUigRQyktq0RCL0Xf1qOJt6pbA7hMrwM3QmY7nUD/No+D6Grzu6m3Mehdu0svdbf2 boQUhth02OR0UVOZpimGgH34q3/byxR9+Z+QNBnAqwgnHefRGVbvLX3Sjd4DXwFf+/bB F3KCrywRaNfMU5rDJK4vJgnWqa2/TQWp24lQzwKbwsLwdjqV7nJLT1HXMSVUadHg2mfA PiEGZi0C9HjPj5YUOw7HFGQa5KnrXlJp5/SANvldmVZE/h9ErQLwk2xL/wFh+bgu2lBW uZZIz/XBrTItA2pmhxKv8qq0IMwH07HJ1h3kel7nIJX8ltdXrTuo9Zvt1CeLwQYUQkF8 U5ng== X-Gm-Message-State: AOAM532XyGSfvB5bvxt6rn5XT6JgBYnbsRJ2f5Xxefz0bTh2MGCAevy9 DUJkmHPBnYlXV0P7onR+Oojd2g== X-Google-Smtp-Source: ABdhPJwjvARjWp99oCCyZPWoVuh4s23ihuzY14iCUMYV+JujvfG/DTj9OwPOJkU7TtBfEtOviI3G4w== X-Received: by 2002:a63:d74e:: with SMTP id w14mr1033004pgi.344.1621279081961; Mon, 17 May 2021 12:18:01 -0700 (PDT) Received: from localhost.localdomain ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id v11sm624466pgs.6.2021.05.17.12.17.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 12:18:01 -0700 (PDT) From: Lance Richardson To: Ajit Khaparde , Somnath Kotur Cc: stable@dpdk.org, Andy Gospodarek Date: Mon, 17 May 2021 15:10:45 -0400 Message-Id: <20210517191046.42686-2-lance.richardson@broadcom.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210517191046.42686-1-lance.richardson@broadcom.com> References: <20210517191046.42686-1-lance.richardson@broadcom.com> MIME-Version: 1.0 Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="000000000000c8faff05c28b739a" X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: [dpdk-stable] [PATCH 20.11 1/2] net/bnxt: fix Rx descriptor status X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" --000000000000c8faff05c28b739a Content-Transfer-Encoding: 8bit [ upstream commit 25fefa2b1760a5feb8762fa12845982b98d91f3d ] Fix a number of issues in the bnxt receive descriptor status function, including: - Provide status of receive descriptor instead of completion descriptor. - Remove invalid comparison of raw ring index with masked ring index. - Correct misinterpretation of offset parameter as ring index. - Correct misuse of completion ring index for mbuf ring (the two rings have different sizes). Fixes: 0fe613bb87b2 ("net/bnxt: support Rx descriptor status") Cc: stable@dpdk.org Signed-off-by: Lance Richardson Reviewed-by: Andy Gospodarek Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/bnxt_ethdev.c | 111 ++++++++++++++++++++++++++------- 1 file changed, 89 insertions(+), 22 deletions(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index fcb6e9963..6732251ff 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -2963,42 +2963,109 @@ bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) static int bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) { - struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; - struct bnxt_rx_ring_info *rxr; + struct bnxt_rx_queue *rxq = rx_queue; struct bnxt_cp_ring_info *cpr; - struct rte_mbuf *rx_buf; + struct bnxt_rx_ring_info *rxr; + uint32_t desc, raw_cons; + struct bnxt *bp = rxq->bp; struct rx_pkt_cmpl *rxcmp; - uint32_t cons, cp_cons; int rc; - if (!rxq) - return -EINVAL; - - rc = is_bnxt_in_error(rxq->bp); + rc = is_bnxt_in_error(bp); if (rc) return rc; - cpr = rxq->cp_ring; - rxr = rxq->rx_ring; - if (offset >= rxq->nb_rx_desc) return -EINVAL; - cons = RING_CMP(cpr->cp_ring_struct, offset); - cp_cons = cpr->cp_raw_cons; - rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; + rxr = rxq->rx_ring; + cpr = rxq->cp_ring; - if (cons > cp_cons) { - if (CMPL_VALID(rxcmp, cpr->valid)) - return RTE_ETH_RX_DESC_DONE; - } else { - if (CMPL_VALID(rxcmp, !cpr->valid)) + /* + * For the vector receive case, the completion at the requested + * offset can be indexed directly. + */ +#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) + if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) { + struct rx_pkt_cmpl *rxcmp; + uint32_t cons; + + /* Check status of completion descriptor. */ + raw_cons = cpr->cp_raw_cons + + offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2); + cons = RING_CMP(cpr->cp_ring_struct, raw_cons); + rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; + + if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) return RTE_ETH_RX_DESC_DONE; + + /* Check whether rx desc has an mbuf attached. */ + cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2); + if (cons >= rxq->rxrearm_start && + cons < rxq->rxrearm_start + rxq->rxrearm_nb) { + return RTE_ETH_RX_DESC_UNAVAIL; + } + + return RTE_ETH_RX_DESC_AVAIL; } - rx_buf = rxr->rx_buf_ring[cons]; - if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf) - return RTE_ETH_RX_DESC_UNAVAIL; +#endif + + /* + * For the non-vector receive case, scan the completion ring to + * locate the completion descriptor for the requested offset. + */ + raw_cons = cpr->cp_raw_cons; + desc = 0; + while (1) { + uint32_t agg_cnt, cons, cmpl_type; + + cons = RING_CMP(cpr->cp_ring_struct, raw_cons); + rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; + + if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) + break; + + cmpl_type = CMP_TYPE(rxcmp); + + switch (cmpl_type) { + case CMPL_BASE_TYPE_RX_L2: + case CMPL_BASE_TYPE_RX_L2_V2: + if (desc == offset) { + cons = rxcmp->opaque; + if (rxr->rx_buf_ring[cons]) + return RTE_ETH_RX_DESC_DONE; + else + return RTE_ETH_RX_DESC_UNAVAIL; + } + agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); + raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; + desc++; + break; + + case CMPL_BASE_TYPE_RX_TPA_END: + if (desc == offset) + return RTE_ETH_RX_DESC_DONE; + + if (BNXT_CHIP_THOR(rxq->bp)) { + struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; + + p5_tpa_end = (void *)rxcmp; + agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); + } else { + struct rx_tpa_end_cmpl *tpa_end; + + tpa_end = (void *)rxcmp; + agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); + } + raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; + desc++; + break; + + default: + raw_cons += CMP_LEN(cmpl_type); + } + } return RTE_ETH_RX_DESC_AVAIL; } -- 2.25.1 --000000000000c8faff05c28b739a--