From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BCE48A0C3F for ; Sat, 12 Jun 2021 01:20:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B5DC5410FE; Sat, 12 Jun 2021 01:20:23 +0200 (CEST) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2072.outbound.protection.outlook.com [40.107.92.72]) by mails.dpdk.org (Postfix) with ESMTP id C1BD341100 for ; Sat, 12 Jun 2021 01:20:20 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VhQcqjtBdKRHpM9BkHdg9sNEqg+dd1oeEcYufAff5Fpg5SyABpx6rtkzmC8aSucVBA3eeVtVHB/IlUfvFuC1IMvhuAlhWz0tS0HUCBHKl0MFWTy4Nbw+Gg70rqDTTV6Cr0Yolv0QhKnvrH/SbrqvVhqcfO2suyM9vmXKKZ59ttupN9tcvVGKIpzqW+KK7isdKko2nVpTwRGaIQJpcO3NZUlW77nXOuEhoIvkG+/eR0JAYzgmdk5S8tSl0Q/fA8eTnTkISLm3SNOI4HbsuSnYdclURjhNVsW6MyJ/qfTdaDyWE6gBb/XruAUuPULDpAj403v3ppNGkVXnqEfd32xNvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=G3wxG+tdbvnEW9bLjwBpjp1juavAnLTuHKy5stmOkjE=; b=mvIjmATs+jrVbK7q9ZF9oFgqKQSQBNNONVBBCfsY+YP2A0Ml6TNMh5kVj+J8wlPkGceATT66sHP9hgdGrk1+gF0nN+TLVb4FQnz08/W5h6+wJqlzfYMdqNpT1u0HBH1Xe58xyqzsLiXt9sj64sdD0LSmi0HOvyVD1hzkwAM0soyj+V86vcuLTPCAleVCdFAdcEeasBjjlUNn4JphsAMBz65HSsCNjEKZE9qRAn6xr4bqP+LxO0uTYfbFOEtPLJWiihS0cL5ACuRz+QNuaBTipqIwV4lioecLLnvusOLZGu18Ud+7D65/KSHISA7viEyeC7JhScbnOfOlhay3SkJw6g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=G3wxG+tdbvnEW9bLjwBpjp1juavAnLTuHKy5stmOkjE=; b=jnH0HbNTuW43KNSKatgcA3+0YH+yuLmpY00Y6cOVJXn8i/YbOIt3SDF9AnvQ4IpCJQLeEfrdIfBeSguuAib4uu62wxVFvpj9OdIT6iLEh0SVmK+GqR1q/cXq4Gr/04PIN8c2wg76Wn7V+yD1exJtxh1vUH5U5SbZtNT8PH7QG8wZAzke7oQdss0VipLBw1MHMhbZQDgAsBG+xSj6okzcmXqyZ1TNvjxNdxG+jlhKtbl2UIaSACBiu79jgjbQI+usVU3mfEPbfx4Cmmp9vgF9QBIhtq8qr+kzWA2eBHfrWoYXCDUy344kw/lwqkwIFL+Q2o5dMh50/yJQsfs7grvnMw== Received: from DM3PR12CA0138.namprd12.prod.outlook.com (2603:10b6:0:51::34) by CH2PR12MB4229.namprd12.prod.outlook.com (2603:10b6:610:a5::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.21; Fri, 11 Jun 2021 23:20:19 +0000 Received: from DM6NAM11FT063.eop-nam11.prod.protection.outlook.com (2603:10b6:0:51:cafe::6c) by DM3PR12CA0138.outlook.office365.com (2603:10b6:0:51::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.20 via Frontend Transport; Fri, 11 Jun 2021 23:20:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT063.mail.protection.outlook.com (10.13.172.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4219.21 via Frontend Transport; Fri, 11 Jun 2021 23:20:19 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Jun 2021 23:20:17 +0000 From: Xueming Li To: Suanming Mou CC: Luca Boccassi , Matan Azrad , "dpdk stable" Date: Sat, 12 Jun 2021 07:04:18 +0800 Message-ID: <20210611230433.8208-164-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210611230433.8208-1-xuemingl@nvidia.com> References: <20210510160258.30982-229-xuemingl@nvidia.com> <20210611230433.8208-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b95dc71c-7db0-4185-d180-08d92d2f7ae3 X-MS-TrafficTypeDiagnostic: CH2PR12MB4229: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2bo/n6L+WWzM/G8byJ4ZQ5diiiUtAEtfR2AU4MMR+NN2E0/qa4o6sIa8t/SOWFl6CvSScsMeg+N337vvBmIUiyTjt+y50pwTQ/73cHyZlDusB7bLByfq2aB2jL20PvSJJl2/m5ahLQ9z98HVL2bnUXHm9/3G5yAmpsvQ/tBknMpVOYBf6ZxDcyrNtSu97xi73eVzWGAD5QMkQ1erBTVBnPETvfW9LZCXH890wYWYgDLjBUg9u9YBzwWk0K9r8+pW3Yz5n1PFx83eJnbVLcxxduE/Dp9RugPigVV3K+N7PRFfMthws/BO8s/YZgvGTps+Q67UtEhY2AoLpLS0R08M5K1+1ZQakcSUIwS6jP/66lkwhdHEp+u4TUGMlQH25FB0OzzmqBhY4fNNnwMcJU45Hx12YImQaTtNLWbe1acaojdoLDDGRc/fP6VJ5su8gtqEFHhOzldfWH1uCmupJSYT+n05kC29P4skIqMAlssehzlrLkY4nQF2mwItM+B2IF01FkpcTl+8Ncpt9R2M4sBvJGtOEVXPAL+Vcfah3kZrtva1NfelJrs/0FEMV4VeAuXxvYGNKgp9bS547MWWeEqkqPygbNIwvp7phC2a0mEmuHyCKOUTBUq5XbhU1hrPPAl96jJNTItBeqUPjTj6GDiMwziYjdTwaSylIJ6/hevy1lWwXlNaCkYxpF6eNu46t5i7ej1VOWSstBAeu768YhKBhKVwhv5gtgw6iWnIn6w2FLbRHjO8nrBE0SpCM88R0SxZ8WUiVNwBVFOleVoELgX6aJapCUccjlrtaSYrQ22keP51gUfrkqIfUSvxnOlUxjFU X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(376002)(39860400002)(136003)(396003)(346002)(36840700001)(46966006)(70586007)(2616005)(8936002)(53546011)(7696005)(82310400003)(70206006)(36860700001)(336012)(1076003)(426003)(86362001)(8676002)(4326008)(7636003)(316002)(37006003)(5660300002)(54906003)(6862004)(83380400001)(36756003)(47076005)(2906002)(186003)(26005)(478600001)(16526019)(966005)(356005)(82740400003)(6286002)(6636002)(55016002)(36906005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2021 23:20:19.6949 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b95dc71c-7db0-4185-d180-08d92d2f7ae3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4229 Subject: [dpdk-stable] patch 'net/mlx5: fix counter offset detection' has been queued to stable release 20.11.2 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 20.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 06/14/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/d565e160b11fff3c4c9c7e1c74cd81b76740153a Thanks. Xueming Li --- >From d565e160b11fff3c4c9c7e1c74cd81b76740153a Mon Sep 17 00:00:00 2001 From: Suanming Mou Date: Thu, 13 May 2021 11:05:15 +0300 Subject: [PATCH] net/mlx5: fix counter offset detection Cc: Luca Boccassi [ upstream commit 4fd5e14848871a682840642fdd6ad776d0017080 ] Currently, the counter offset support is discovered by creating the rule with invalid offset counter and drop action in root table. If the rule creation fails with EINVAL errno, that mean counter offset is not supported in root table. However, drop action may not be supported in some rdma-core version in root table. In this case, the discover code will not work properly. This commits changes flow attribute to egress. That removes all the extra fate actions in the flow to avoid any unsupported fate actions make the discover code fail time to time. Fixes: 994829e695c0 ("net/mlx5: remove single counter container") Signed-off-by: Suanming Mou Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_flow_dv.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 5a5a33172a..f5ceb7a2d5 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -12585,7 +12585,7 @@ mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev) .size = sizeof(value.buf), }; struct mlx5dv_flow_matcher_attr dv_attr = { - .type = IBV_FLOW_ATTR_NORMAL, + .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS, .priority = 0, .match_criteria_enable = 0, .match_mask = (void *)&mask, @@ -12597,7 +12597,7 @@ mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev) void *flow = NULL; int ret = -1; - tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL); + tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL, 0, 0, NULL); if (!tbl) goto err; dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4); @@ -12607,14 +12607,12 @@ mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev) &actions[0]); if (ret) goto err; - actions[1] = sh->dr_drop_action ? sh->dr_drop_action : - priv->drop_queue.hrxq->action; dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf); ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj, &matcher); if (ret) goto err; - ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2, + ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1, actions, &flow); err: /* -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-06-12 06:54:00.697750300 +0800 +++ 0164-net-mlx5-fix-counter-offset-detection.patch 2021-06-12 06:53:56.650000000 +0800 @@ -1 +1 @@ -From 4fd5e14848871a682840642fdd6ad776d0017080 Mon Sep 17 00:00:00 2001 +From d565e160b11fff3c4c9c7e1c74cd81b76740153a Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Luca Boccassi + +[ upstream commit 4fd5e14848871a682840642fdd6ad776d0017080 ] @@ -19 +21,0 @@ -Cc: stable@dpdk.org @@ -28 +30 @@ -index 7fc7efbc5c..71d9f88a95 100644 +index 5a5a33172a..f5ceb7a2d5 100644 @@ -31 +33 @@ -@@ -16081,7 +16081,7 @@ mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev) +@@ -12585,7 +12585,7 @@ mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev) @@ -40 +42 @@ -@@ -16093,7 +16093,7 @@ mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev) +@@ -12597,7 +12597,7 @@ mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev) @@ -44,3 +46,2 @@ -- tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, -+ tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL, - 0, 0, 0, NULL); +- tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL); ++ tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL, 0, 0, NULL); @@ -49 +50,2 @@ -@@ -16104,14 +16104,12 @@ mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev) + dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4); +@@ -12607,14 +12607,12 @@ mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)