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huawei.com; dkim=none (message not signed) header.d=none;huawei.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT013.mail.protection.outlook.com (10.13.174.227) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4219.21 via Frontend Transport; Fri, 11 Jun 2021 23:09:56 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Jun 2021 23:09:54 +0000 From: Xueming Li To: Chengwen Feng CC: Luca Boccassi , Min Hu , dpdk stable Date: Sat, 12 Jun 2021 07:02:29 +0800 Message-ID: <20210611230433.8208-55-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210611230433.8208-1-xuemingl@nvidia.com> References: <20210510160258.30982-229-xuemingl@nvidia.com> <20210611230433.8208-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5ae6c7f8-6e5e-4e9d-f2da-08d92d2e078f X-MS-TrafficTypeDiagnostic: BYAPR12MB2871: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2582; 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SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(396003)(39860400002)(346002)(376002)(36840700001)(46966006)(6666004)(54906003)(7696005)(53546011)(6916009)(356005)(316002)(8676002)(36860700001)(8936002)(86362001)(47076005)(7636003)(36906005)(6286002)(1076003)(4326008)(55016002)(2906002)(83380400001)(82740400003)(36756003)(2616005)(336012)(426003)(30864003)(70586007)(5660300002)(70206006)(26005)(16526019)(186003)(478600001)(966005)(82310400003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2021 23:09:56.7236 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ae6c7f8-6e5e-4e9d-f2da-08d92d2e078f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2871 Subject: [dpdk-stable] patch 'net/hns3: fix time delta calculation' has been queued to stable release 20.11.2 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 20.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 06/14/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/2f0e34a575054004ea24598e1526f63f88c1a695 Thanks. Xueming Li --- >From 2f0e34a575054004ea24598e1526f63f88c1a695 Mon Sep 17 00:00:00 2001 From: Chengwen Feng Date: Wed, 28 Apr 2021 15:20:53 +0800 Subject: [PATCH] net/hns3: fix time delta calculation Cc: Luca Boccassi [ upstream commit 78dbb6f999314ae05c2f5fb617660ec020a5309c ] Currently, driver uses gettimeofday() API to get the time, and then calculate the time delta, the delta will be used mainly in judging timeout process. But the time which gets from gettimeofday() API isn't monotonically increasing. The process may fail if the system time is changed. We use the following scheme to fix it: 1. Add hns3_clock_gettime() API which will get the monotonically increasing time. 2. Add hns3_clock_calctime_ms() API which will get the milliseconds of the monotonically increasing time. 3. Add hns3_clock_calctime_ms() API which will calc the milliseconds of a given time. Fixes: 2790c6464725 ("net/hns3: support device reset") Signed-off-by: Chengwen Feng Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_ethdev.c | 46 ++++++++++++++++++++++++++----- drivers/net/hns3/hns3_ethdev.h | 12 ++------ drivers/net/hns3/hns3_ethdev_vf.c | 11 ++++---- drivers/net/hns3/hns3_intr.c | 34 +++++++++++------------ 4 files changed, 63 insertions(+), 40 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index a347533a94..907435c677 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -5491,7 +5491,7 @@ hns3_wait_hardware_ready(struct hns3_adapter *hns) if (wait_data->result == HNS3_WAIT_SUCCESS) return 0; else if (wait_data->result == HNS3_WAIT_TIMEOUT) { - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", tv.tv_sec, tv.tv_usec); return -ETIME; @@ -5501,7 +5501,7 @@ hns3_wait_hardware_ready(struct hns3_adapter *hns) wait_data->hns = hns; wait_data->check_completion = is_pf_reset_done; wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT * - HNS3_RESET_WAIT_MS + get_timeofday_ms(); + HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms(); wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC; wait_data->count = HNS3_RESET_WAIT_CNT; wait_data->result = HNS3_WAIT_REQUEST; @@ -5540,7 +5540,7 @@ hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) struct timeval tv; uint32_t val; - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) || hns3_read_dev(hw, HNS3_FUN_RST_ING)) { hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld", @@ -5834,12 +5834,11 @@ hns3_reset_service(void *param) */ reset_level = hns3_get_reset_level(hns, &hw->reset.pending); if (reset_level != HNS3_NONE_RESET) { - gettimeofday(&tv_start, NULL); + hns3_clock_gettime(&tv_start); ret = hns3_reset_process(hns, reset_level); - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); timersub(&tv, &tv_start, &tv_delta); - msec = tv_delta.tv_sec * MSEC_PER_SEC + - tv_delta.tv_usec / USEC_PER_MSEC; + msec = hns3_clock_calctime_ms(&tv_delta); if (msec > HNS3_RESET_PROCESS_MS) hns3_err(hw, "%d handle long time delta %" PRIu64 " ms time=%ld.%.6ld", @@ -6183,6 +6182,39 @@ hns3_query_dev_fec_info(struct hns3_hw *hw) return ret; } +void +hns3_clock_gettime(struct timeval *tv) +{ +#ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */ +#define CLOCK_TYPE CLOCK_MONOTONIC_RAW +#else +#define CLOCK_TYPE CLOCK_MONOTONIC +#endif +#define NSEC_TO_USEC_DIV 1000 + + struct timespec spec; + (void)clock_gettime(CLOCK_TYPE, &spec); + + tv->tv_sec = spec.tv_sec; + tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV; +} + +uint64_t +hns3_clock_calctime_ms(struct timeval *tv) +{ + return (uint64_t)tv->tv_sec * MSEC_PER_SEC + + tv->tv_usec / USEC_PER_MSEC; +} + +uint64_t +hns3_clock_gettime_ms(void) +{ + struct timeval tv; + + hns3_clock_gettime(&tv); + return hns3_clock_calctime_ms(&tv); +} + static const struct eth_dev_ops hns3_eth_dev_ops = { .dev_configure = hns3_dev_configure, .dev_start = hns3_dev_start, diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 5d76012eea..3032af6f55 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -908,15 +908,9 @@ static inline uint32_t hns3_read_reg(void *base, uint32_t reg) #define MSEC_PER_SEC 1000L #define USEC_PER_MSEC 1000L -static inline uint64_t -get_timeofday_ms(void) -{ - struct timeval tv; - - (void)gettimeofday(&tv, NULL); - - return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; -} +void hns3_clock_gettime(struct timeval *tv); +uint64_t hns3_clock_calctime_ms(struct timeval *tv); +uint64_t hns3_clock_gettime_ms(void); static inline uint64_t hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 20da418ba9..8ad02a0b11 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2370,7 +2370,7 @@ hns3vf_wait_hardware_ready(struct hns3_adapter *hns) hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete"); return -EAGAIN; } else if (wait_data->result == HNS3_WAIT_TIMEOUT) { - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", tv.tv_sec, tv.tv_usec); return -ETIME; @@ -2380,7 +2380,7 @@ hns3vf_wait_hardware_ready(struct hns3_adapter *hns) wait_data->hns = hns; wait_data->check_completion = is_vf_reset_done; wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT * - HNS3VF_RESET_WAIT_MS + get_timeofday_ms(); + HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms(); wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC; wait_data->count = HNS3VF_RESET_WAIT_CNT; wait_data->result = HNS3_WAIT_REQUEST; @@ -2626,12 +2626,11 @@ hns3vf_reset_service(void *param) */ reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); if (reset_level != HNS3_NONE_RESET) { - gettimeofday(&tv_start, NULL); + hns3_clock_gettime(&tv_start); hns3_reset_process(hns, reset_level); - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); timersub(&tv, &tv_start, &tv_delta); - msec = tv_delta.tv_sec * MSEC_PER_SEC + - tv_delta.tv_usec / USEC_PER_MSEC; + msec = hns3_clock_calctime_ms(&tv_delta); if (msec > HNS3_RESET_PROCESS_MS) hns3_err(hw, "%d handle long time delta %" PRIu64 " ms time=%ld.%.6ld", diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index dce9f36e6d..4abcd7898e 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -1829,7 +1829,7 @@ hns3_wait_callback(void *param) * Check if the current time exceeds the deadline * or a pending reset coming, or reset during close. */ - msec = get_timeofday_ms(); + msec = hns3_clock_gettime_ms(); if (msec > data->end_ms || is_reset_pending(hns) || hw->adapter_state == HNS3_NIC_CLOSING) { done = false; @@ -2014,7 +2014,7 @@ hns3_reset_pre(struct hns3_adapter *hns) rte_atomic16_set(&hns->hw.reset.resetting, 1); hw->reset.stage = RESET_STAGE_DOWN; ret = hw->reset.ops->stop_service(hns); - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); if (ret) { hns3_warn(hw, "Reset step1 down fail=%d time=%ld.%.6ld", ret, tv.tv_sec, tv.tv_usec); @@ -2026,7 +2026,7 @@ hns3_reset_pre(struct hns3_adapter *hns) } if (hw->reset.stage == RESET_STAGE_PREWAIT) { ret = hw->reset.ops->prepare_reset(hns); - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); if (ret) { hns3_warn(hw, "Reset step2 prepare wait fail=%d time=%ld.%.6ld", @@ -2064,7 +2064,7 @@ hns3_reset_post(struct hns3_adapter *hns) } ret = hw->reset.ops->reinit_dev(hns); rte_spinlock_unlock(&hw->lock); - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); if (ret) { hns3_warn(hw, "Reset step5 devinit fail=%d retries=%d", ret, hw->reset.retries); @@ -2082,7 +2082,7 @@ hns3_reset_post(struct hns3_adapter *hns) rte_spinlock_lock(&hw->lock); ret = hw->reset.ops->restore_conf(hns); rte_spinlock_unlock(&hw->lock); - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); if (ret) { hns3_warn(hw, "Reset step6 restore fail=%d retries=%d", @@ -2105,7 +2105,7 @@ hns3_reset_post(struct hns3_adapter *hns) rte_spinlock_lock(&hw->lock); hw->reset.ops->start_service(hns); rte_spinlock_unlock(&hw->lock); - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); timersub(&tv, &hw->reset.start_time, &tv_delta); hns3_warn(hw, "%s reset done fail_cnt:%" PRIx64 " success_cnt:%" PRIx64 " global_cnt:%" PRIx64 @@ -2117,10 +2117,9 @@ hns3_reset_post(struct hns3_adapter *hns) hw->reset.stats.request_cnt, hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt); hns3_warn(hw, - "%s reset done delta %ld ms time=%ld.%.6ld", + "%s reset done delta %" PRIu64 " ms time=%ld.%.6ld", reset_string[hw->reset.level], - tv_delta.tv_sec * MSEC_PER_SEC + - tv_delta.tv_usec / USEC_PER_MSEC, + hns3_clock_calctime_ms(&tv_delta), tv.tv_sec, tv.tv_usec); hw->reset.level = HNS3_NONE_RESET; } @@ -2160,7 +2159,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) if (hw->reset.level == HNS3_NONE_RESET) { hw->reset.level = new_level; hw->reset.stats.exec_cnt++; - gettimeofday(&hw->reset.start_time, NULL); + hns3_clock_gettime(&hw->reset.start_time); hns3_warn(hw, "Start %s reset time=%ld.%.6ld", reset_string[hw->reset.level], hw->reset.start_time.tv_sec, @@ -2168,7 +2167,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) } if (is_reset_pending(hns)) { - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); hns3_warn(hw, "%s reset is aborted by high level time=%ld.%.6ld", reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec); @@ -2186,7 +2185,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) ret = hns3_reset_req_hw_reset(hns); if (ret == -EAGAIN) return ret; - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); hns3_warn(hw, "Reset step3 request IMP reset success time=%ld.%.6ld", tv.tv_sec, tv.tv_usec); @@ -2197,7 +2196,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) ret = hw->reset.ops->wait_hardware_ready(hns); if (ret) goto retry; - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); hns3_warn(hw, "Reset step4 reset wait success time=%ld.%.6ld", tv.tv_sec, tv.tv_usec); hw->reset.stage = RESET_STAGE_DEV_INIT; @@ -2225,12 +2224,11 @@ err: rte_spinlock_unlock(&hw->lock); rte_atomic16_clear(&hns->hw.reset.resetting); hw->reset.stage = RESET_STAGE_NONE; - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); timersub(&tv, &hw->reset.start_time, &tv_delta); - hns3_warn(hw, "%s reset fail delta %ld ms time=%ld.%.6ld", + hns3_warn(hw, "%s reset fail delta %" PRIu64 " ms time=%ld.%.6ld", reset_string[hw->reset.level], - tv_delta.tv_sec * MSEC_PER_SEC + - tv_delta.tv_usec / USEC_PER_MSEC, + hns3_clock_calctime_ms(&tv_delta), tv.tv_sec, tv.tv_usec); hw->reset.level = HNS3_NONE_RESET; } @@ -2262,7 +2260,7 @@ hns3_reset_abort(struct hns3_adapter *hns) rte_eal_alarm_cancel(hns3_wait_callback, hw->reset.wait_data); if (hw->reset.level != HNS3_NONE_RESET) { - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); hns3_err(hw, "Failed to terminate reset: %s time=%ld.%.6ld", reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec); } -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-06-12 06:53:58.075185900 +0800 +++ 0055-net-hns3-fix-time-delta-calculation.patch 2021-06-12 06:53:56.280000000 +0800 @@ -1 +1 @@ -From 78dbb6f999314ae05c2f5fb617660ec020a5309c Mon Sep 17 00:00:00 2001 +From 2f0e34a575054004ea24598e1526f63f88c1a695 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Luca Boccassi + +[ upstream commit 78dbb6f999314ae05c2f5fb617660ec020a5309c ] @@ -22 +24,0 @@ -Cc: stable@dpdk.org @@ -34 +36 @@ -index 02637e497b..b6655549e9 100644 +index a347533a94..907435c677 100644 @@ -37 +39 @@ -@@ -6346,7 +6346,7 @@ hns3_wait_hardware_ready(struct hns3_adapter *hns) +@@ -5491,7 +5491,7 @@ hns3_wait_hardware_ready(struct hns3_adapter *hns) @@ -46 +48 @@ -@@ -6356,7 +6356,7 @@ hns3_wait_hardware_ready(struct hns3_adapter *hns) +@@ -5501,7 +5501,7 @@ hns3_wait_hardware_ready(struct hns3_adapter *hns) @@ -55 +57 @@ -@@ -6395,7 +6395,7 @@ hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) +@@ -5540,7 +5540,7 @@ hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) @@ -64 +66 @@ -@@ -6703,12 +6703,11 @@ hns3_reset_service(void *param) +@@ -5834,12 +5834,11 @@ hns3_reset_service(void *param) @@ -80,2 +82,2 @@ -@@ -7208,6 +7207,39 @@ hns3_get_module_info(struct rte_eth_dev *dev, - return 0; +@@ -6183,6 +6182,39 @@ hns3_query_dev_fec_info(struct hns3_hw *hw) + return ret; @@ -117,3 +119,3 @@ - static int - hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args) - { + static const struct eth_dev_ops hns3_eth_dev_ops = { + .dev_configure = hns3_dev_configure, + .dev_start = hns3_dev_start, @@ -121 +123 @@ -index ba50e70650..b2dacb9771 100644 +index 5d76012eea..3032af6f55 100644 @@ -124 +126 @@ -@@ -1022,15 +1022,9 @@ static inline uint32_t hns3_read_reg(void *base, uint32_t reg) +@@ -908,15 +908,9 @@ static inline uint32_t hns3_read_reg(void *base, uint32_t reg) @@ -144 +146 @@ -index fcdf0e3e7b..9a85e970ce 100644 +index 20da418ba9..8ad02a0b11 100644 @@ -147 +149 @@ -@@ -2510,7 +2510,7 @@ hns3vf_wait_hardware_ready(struct hns3_adapter *hns) +@@ -2370,7 +2370,7 @@ hns3vf_wait_hardware_ready(struct hns3_adapter *hns) @@ -156 +158 @@ -@@ -2520,7 +2520,7 @@ hns3vf_wait_hardware_ready(struct hns3_adapter *hns) +@@ -2380,7 +2380,7 @@ hns3vf_wait_hardware_ready(struct hns3_adapter *hns) @@ -165 +167 @@ -@@ -2775,12 +2775,11 @@ hns3vf_reset_service(void *param) +@@ -2626,12 +2626,11 @@ hns3vf_reset_service(void *param) @@ -182 +184 @@ -index cc7d7c6392..ba6a044323 100644 +index dce9f36e6d..4abcd7898e 100644 @@ -185 +187 @@ -@@ -2465,7 +2465,7 @@ hns3_wait_callback(void *param) +@@ -1829,7 +1829,7 @@ hns3_wait_callback(void *param) @@ -194,2 +196,2 @@ -@@ -2650,7 +2650,7 @@ hns3_reset_pre(struct hns3_adapter *hns) - __atomic_store_n(&hns->hw.reset.resetting, 1, __ATOMIC_RELAXED); +@@ -2014,7 +2014,7 @@ hns3_reset_pre(struct hns3_adapter *hns) + rte_atomic16_set(&hns->hw.reset.resetting, 1); @@ -203 +205 @@ -@@ -2662,7 +2662,7 @@ hns3_reset_pre(struct hns3_adapter *hns) +@@ -2026,7 +2026,7 @@ hns3_reset_pre(struct hns3_adapter *hns) @@ -212 +214 @@ -@@ -2700,7 +2700,7 @@ hns3_reset_post(struct hns3_adapter *hns) +@@ -2064,7 +2064,7 @@ hns3_reset_post(struct hns3_adapter *hns) @@ -221 +223 @@ -@@ -2718,7 +2718,7 @@ hns3_reset_post(struct hns3_adapter *hns) +@@ -2082,7 +2082,7 @@ hns3_reset_post(struct hns3_adapter *hns) @@ -230 +232 @@ -@@ -2741,7 +2741,7 @@ hns3_reset_post(struct hns3_adapter *hns) +@@ -2105,7 +2105,7 @@ hns3_reset_post(struct hns3_adapter *hns) @@ -239 +241 @@ -@@ -2753,10 +2753,9 @@ hns3_reset_post(struct hns3_adapter *hns) +@@ -2117,10 +2117,9 @@ hns3_reset_post(struct hns3_adapter *hns) @@ -252 +254 @@ -@@ -2796,7 +2795,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) +@@ -2160,7 +2159,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) @@ -261 +263 @@ -@@ -2804,7 +2803,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) +@@ -2168,7 +2167,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) @@ -270 +272 @@ -@@ -2822,7 +2821,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) +@@ -2186,7 +2185,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) @@ -279 +281 @@ -@@ -2833,7 +2832,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) +@@ -2197,7 +2196,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) @@ -288 +290 @@ -@@ -2861,12 +2860,11 @@ err: +@@ -2225,12 +2224,11 @@ err: @@ -290 +292 @@ - __atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED); + rte_atomic16_clear(&hns->hw.reset.resetting); @@ -304 +306 @@ -@@ -2898,7 +2896,7 @@ hns3_reset_abort(struct hns3_adapter *hns) +@@ -2262,7 +2260,7 @@ hns3_reset_abort(struct hns3_adapter *hns)