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huawei.com; dkim=none (message not signed) header.d=none;huawei.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT006.mail.protection.outlook.com (10.13.174.246) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4219.21 via Frontend Transport; Fri, 11 Jun 2021 23:10:47 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Jun 2021 23:10:46 +0000 From: Xueming Li To: Chengwen Feng CC: Luca Boccassi , Min Hu , dpdk stable Date: Sat, 12 Jun 2021 07:02:37 +0800 Message-ID: <20210611230433.8208-63-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210611230433.8208-1-xuemingl@nvidia.com> References: <20210510160258.30982-229-xuemingl@nvidia.com> <20210611230433.8208-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6b7fb7fb-a0e6-409e-381d-08d92d2e25f4 X-MS-TrafficTypeDiagnostic: BN9PR12MB5178: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(39860400002)(346002)(376002)(396003)(136003)(36840700001)(46966006)(2906002)(316002)(5660300002)(54906003)(82310400003)(7696005)(55016002)(83380400001)(6666004)(1076003)(70206006)(36756003)(86362001)(36906005)(966005)(70586007)(7636003)(47076005)(478600001)(36860700001)(26005)(6916009)(8676002)(16526019)(82740400003)(186003)(53546011)(8936002)(6286002)(2616005)(426003)(356005)(4326008)(336012); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2021 23:10:47.6954 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b7fb7fb-a0e6-409e-381d-08d92d2e25f4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5178 Subject: [dpdk-stable] patch 'net/hns3: fix vector Rx burst limitation' has been queued to stable release 20.11.2 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 20.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 06/14/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/29da2a8b3d1e2989336fe05798677eba797e2034 Thanks. Xueming Li --- >From 29da2a8b3d1e2989336fe05798677eba797e2034 Mon Sep 17 00:00:00 2001 From: Chengwen Feng Date: Fri, 30 Apr 2021 14:28:50 +0800 Subject: [PATCH] net/hns3: fix vector Rx burst limitation Cc: Luca Boccassi [ upstream commit 2d408d0609c4b06dbade72e4e6af6c978e96b0de ] Currently, driver uses the macro HNS3_DEFAULT_RX_BURST whose value is 32 to limit the vector Rx burst size, as a result, the burst size can't exceed 32. This patch fixes this problem by support big burst size. Also adjust HNS3_DEFAULT_RX_BURST to 64 as it performs better than 32. Fixes: a3d4f4d291d7 ("net/hns3: support NEON Rx") Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") Signed-off-by: Chengwen Feng Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_rxtx.h | 2 +- drivers/net/hns3/hns3_rxtx_vec.c | 36 +++++++++++++++++++++------- drivers/net/hns3/hns3_rxtx_vec.h | 3 +++ drivers/net/hns3/hns3_rxtx_vec_sve.c | 32 ++++++++++++++++++++----- 4 files changed, 58 insertions(+), 15 deletions(-) diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 46d1b8cb27..dc9c89b5af 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -20,7 +20,7 @@ #define HNS3_DEFAULT_TX_RS_THRESH 32 #define HNS3_TX_FAST_FREE_AHEAD 64 -#define HNS3_DEFAULT_RX_BURST 32 +#define HNS3_DEFAULT_RX_BURST 64 #if (HNS3_DEFAULT_RX_BURST > 64) #error "PMD HNS3: HNS3_DEFAULT_RX_BURST must <= 64\n" #endif diff --git a/drivers/net/hns3/hns3_rxtx_vec.c b/drivers/net/hns3/hns3_rxtx_vec.c index b8ce0ee670..63f910165e 100644 --- a/drivers/net/hns3/hns3_rxtx_vec.c +++ b/drivers/net/hns3/hns3_rxtx_vec.c @@ -104,14 +104,13 @@ hns3_recv_pkts_vec(void *__restrict rx_queue, { struct hns3_rx_queue *rxq = rx_queue; struct hns3_desc *rxdp = &rxq->rx_ring[rxq->next_to_use]; - uint64_t bd_err_mask; /* bit mask indicate whick pkts is error */ + uint64_t pkt_err_mask; /* bit mask indicate whick pkts is error */ uint16_t nb_rx; - nb_pkts = RTE_MIN(nb_pkts, HNS3_DEFAULT_RX_BURST); - nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, HNS3_DEFAULT_DESCS_PER_LOOP); - rte_prefetch_non_temporal(rxdp); + nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, HNS3_DEFAULT_DESCS_PER_LOOP); + if (rxq->rx_rearm_nb > HNS3_DEFAULT_RXQ_REARM_THRESH) hns3_rxq_rearm_mbuf(rxq); @@ -124,10 +123,31 @@ hns3_recv_pkts_vec(void *__restrict rx_queue, rte_prefetch0(rxq->sw_ring[rxq->next_to_use + 2].mbuf); rte_prefetch0(rxq->sw_ring[rxq->next_to_use + 3].mbuf); - bd_err_mask = 0; - nb_rx = hns3_recv_burst_vec(rxq, rx_pkts, nb_pkts, &bd_err_mask); - if (unlikely(bd_err_mask)) - nb_rx = hns3_rx_reassemble_pkts(rx_pkts, nb_rx, bd_err_mask); + if (likely(nb_pkts <= HNS3_DEFAULT_RX_BURST)) { + pkt_err_mask = 0; + nb_rx = hns3_recv_burst_vec(rxq, rx_pkts, nb_pkts, + &pkt_err_mask); + nb_rx = hns3_rx_reassemble_pkts(rx_pkts, nb_rx, pkt_err_mask); + return nb_rx; + } + + nb_rx = 0; + while (nb_pkts > 0) { + uint16_t ret, n; + + n = RTE_MIN(nb_pkts, HNS3_DEFAULT_RX_BURST); + pkt_err_mask = 0; + ret = hns3_recv_burst_vec(rxq, &rx_pkts[nb_rx], n, + &pkt_err_mask); + nb_pkts -= ret; + nb_rx += hns3_rx_reassemble_pkts(&rx_pkts[nb_rx], ret, + pkt_err_mask); + if (ret < n) + break; + + if (rxq->rx_rearm_nb > HNS3_DEFAULT_RXQ_REARM_THRESH) + hns3_rxq_rearm_mbuf(rxq); + } return nb_rx; } diff --git a/drivers/net/hns3/hns3_rxtx_vec.h b/drivers/net/hns3/hns3_rxtx_vec.h index 2baf085b95..67c75e44ef 100644 --- a/drivers/net/hns3/hns3_rxtx_vec.h +++ b/drivers/net/hns3/hns3_rxtx_vec.h @@ -71,6 +71,9 @@ hns3_rx_reassemble_pkts(struct rte_mbuf **rx_pkts, uint16_t count, i; uint64_t mask; + if (likely(pkt_err_mask == 0)) + return nb_pkts; + count = 0; for (i = 0; i < nb_pkts; i++) { mask = ((uint64_t)1u) << i; diff --git a/drivers/net/hns3/hns3_rxtx_vec_sve.c b/drivers/net/hns3/hns3_rxtx_vec_sve.c index 1a28fe0a86..67bf8ccdc5 100644 --- a/drivers/net/hns3/hns3_rxtx_vec_sve.c +++ b/drivers/net/hns3/hns3_rxtx_vec_sve.c @@ -287,12 +287,11 @@ hns3_recv_pkts_vec_sve(void *__restrict rx_queue, { struct hns3_rx_queue *rxq = rx_queue; struct hns3_desc *rxdp = &rxq->rx_ring[rxq->next_to_use]; - uint64_t bd_err_mask; /* bit mask indicate whick pkts is error */ + uint64_t pkt_err_mask; /* bit mask indicate whick pkts is error */ uint16_t nb_rx; rte_prefetch_non_temporal(rxdp); - nb_pkts = RTE_MIN(nb_pkts, HNS3_DEFAULT_RX_BURST); nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, HNS3_SVE_DEFAULT_DESCS_PER_LOOP); if (rxq->rx_rearm_nb > HNS3_DEFAULT_RXQ_REARM_THRESH) @@ -304,10 +303,31 @@ hns3_recv_pkts_vec_sve(void *__restrict rx_queue, hns3_rx_prefetch_mbuf_sve(&rxq->sw_ring[rxq->next_to_use]); - bd_err_mask = 0; - nb_rx = hns3_recv_burst_vec_sve(rxq, rx_pkts, nb_pkts, &bd_err_mask); - if (unlikely(bd_err_mask)) - nb_rx = hns3_rx_reassemble_pkts(rx_pkts, nb_rx, bd_err_mask); + if (likely(nb_pkts <= HNS3_DEFAULT_RX_BURST)) { + pkt_err_mask = 0; + nb_rx = hns3_recv_burst_vec_sve(rxq, rx_pkts, nb_pkts, + &pkt_err_mask); + nb_rx = hns3_rx_reassemble_pkts(rx_pkts, nb_rx, pkt_err_mask); + return nb_rx; + } + + nb_rx = 0; + while (nb_pkts > 0) { + uint16_t ret, n; + + n = RTE_MIN(nb_pkts, HNS3_DEFAULT_RX_BURST); + pkt_err_mask = 0; + ret = hns3_recv_burst_vec_sve(rxq, &rx_pkts[nb_rx], n, + &pkt_err_mask); + nb_pkts -= ret; + nb_rx += hns3_rx_reassemble_pkts(&rx_pkts[nb_rx], ret, + pkt_err_mask); + if (ret < n) + break; + + if (rxq->rx_rearm_nb > HNS3_DEFAULT_RXQ_REARM_THRESH) + hns3_rxq_rearm_mbuf_sve(rxq); + } return nb_rx; } -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-06-12 06:53:58.260711200 +0800 +++ 0063-net-hns3-fix-vector-Rx-burst-limitation.patch 2021-06-12 06:53:56.300000000 +0800 @@ -1 +1 @@ -From 2d408d0609c4b06dbade72e4e6af6c978e96b0de Mon Sep 17 00:00:00 2001 +From 29da2a8b3d1e2989336fe05798677eba797e2034 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Luca Boccassi + +[ upstream commit 2d408d0609c4b06dbade72e4e6af6c978e96b0de ] @@ -15 +17,0 @@ -Cc: stable@dpdk.org @@ -27 +29 @@ -index 1e2e994d2b..ba24e0076a 100644 +index 46d1b8cb27..dc9c89b5af 100644 @@ -40 +42 @@ -index dc1e1ae57b..cc8b9706a8 100644 +index b8ce0ee670..63f910165e 100644 @@ -43 +45 @@ -@@ -108,14 +108,13 @@ hns3_recv_pkts_vec(void *__restrict rx_queue, +@@ -104,14 +104,13 @@ hns3_recv_pkts_vec(void *__restrict rx_queue, @@ -61 +63 @@ -@@ -128,10 +127,31 @@ hns3_recv_pkts_vec(void *__restrict rx_queue, +@@ -124,10 +123,31 @@ hns3_recv_pkts_vec(void *__restrict rx_queue, @@ -112 +114 @@ -index ef6c875c80..bf7f704006 100644 +index 1a28fe0a86..67bf8ccdc5 100644 @@ -115 +117 @@ -@@ -292,12 +292,11 @@ hns3_recv_pkts_vec_sve(void *__restrict rx_queue, +@@ -287,12 +287,11 @@ hns3_recv_pkts_vec_sve(void *__restrict rx_queue, @@ -129 +131 @@ -@@ -309,10 +308,31 @@ hns3_recv_pkts_vec_sve(void *__restrict rx_queue, +@@ -304,10 +303,31 @@ hns3_recv_pkts_vec_sve(void *__restrict rx_queue,