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From: Ruifeng Wang <ruifeng.wang@arm.com>
To: dev@dpdk.org
Cc: beilei.xing@intel.com, qi.z.zhang@intel.com,
	bruce.richardson@intel.com, jerinj@marvell.com,
	hemant.agrawal@nxp.com, drc@linux.vnet.ibm.com,
	honnappa.nagarahalli@arm.com, stable@dpdk.org, nd@arm.com,
	Ruifeng Wang <ruifeng.wang@arm.com>
Subject: [dpdk-stable] [PATCH 1/2] net/i40e: fix risk in Rx descriptor read in NEON vector path
Date: Mon,  6 Sep 2021 11:32:00 +0800
Message-ID: <20210906033201.1789796-2-ruifeng.wang@arm.com> (raw)
In-Reply-To: <20210906033201.1789796-1-ruifeng.wang@arm.com>

Rx descriptor is 16B/32B in size and consists of multiple words.
The word that includes DD field should be read first. Read result
with DD bit set indicates the rest part in a descriptor is valid.

In NEON vector PMD, vector load loads two contiguous 8B of
descriptor data into vector register. Given vector load ensures no
16B atomicity, read of the word that includes DD field could be
reordered after read of other words. In this case, some words could
be invalid data.

Read barrier is added after read of qword1 that includes DD field.
And qword0 is reloaded to update vector register. This ensures
what fetched is correct descriptor data.

Fixes: ae0eb310f253 ("net/i40e: implement vector PMD for ARM")
Cc: stable@dpdk.org

Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
---
 drivers/net/i40e/i40e_rxtx_vec_neon.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/net/i40e/i40e_rxtx_vec_neon.c b/drivers/net/i40e/i40e_rxtx_vec_neon.c
index b2683fda60..71191c7cc8 100644
--- a/drivers/net/i40e/i40e_rxtx_vec_neon.c
+++ b/drivers/net/i40e/i40e_rxtx_vec_neon.c
@@ -286,6 +286,14 @@ _recv_raw_pkts_vec(struct i40e_rx_queue *__rte_restrict rxq,
 		descs[1] =  vld1q_u64((uint64_t *)(rxdp + 1));
 		descs[0] =  vld1q_u64((uint64_t *)(rxdp));
 
+		/* Use acquire fence to order loads of descriptor qwords */
+		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+		/* A.2 reload qword0 to make it ordered after qword1 load */
+		descs[3] = vld1q_lane_u64((uint64_t *)(rxdp + 3), descs[3], 0);
+		descs[2] = vld1q_lane_u64((uint64_t *)(rxdp + 2), descs[2], 0);
+		descs[1] = vld1q_lane_u64((uint64_t *)(rxdp + 1), descs[1], 0);
+		descs[0] = vld1q_lane_u64((uint64_t *)(rxdp), descs[0], 0);
+
 		/* B.1 load 4 mbuf point */
 		mbp1 = vld1q_u64((uint64_t *)&sw_ring[pos]);
 		mbp2 = vld1q_u64((uint64_t *)&sw_ring[pos + 2]);
-- 
2.25.1


  reply	other threads:[~2021-09-06  3:32 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-06  3:31 [dpdk-stable] [PATCH 0/2] i40e Rx descriptor loads ordering Ruifeng Wang
2021-09-06  3:32 ` Ruifeng Wang [this message]
2021-09-14 18:33   ` [dpdk-stable] [PATCH 1/2] net/i40e: fix risk in Rx descriptor read in NEON vector path Honnappa Nagarahalli
2021-09-15  8:42     ` Ruifeng Wang
2021-09-06  3:32 ` [dpdk-stable] [PATCH 2/2] net/i40e: fix risk in Rx descriptor read in scalar path Ruifeng Wang
2021-09-14 18:06   ` Honnappa Nagarahalli
2021-09-15  8:33 ` [dpdk-stable] [PATCH v2 0/2] i40e Rx descriptor loads ordering Ruifeng Wang
2021-09-15  8:33   ` [dpdk-stable] [PATCH v2 1/2] net/i40e: fix risk in Rx descriptor read in NEON vector path Ruifeng Wang
2021-09-15  8:33   ` [dpdk-stable] [PATCH v2 2/2] net/i40e: fix risk in Rx descriptor read in scalar path Ruifeng Wang
2021-09-29 15:05     ` Ferruh Yigit
2021-09-29 15:29       ` Honnappa Nagarahalli
2021-10-11 16:26         ` Ferruh Yigit
2021-10-19 11:14           ` Zhang, Qi Z
2021-11-05  6:57             ` Ruifeng Wang
2021-11-11 10:27               ` Ruifeng Wang
2021-11-11 12:27     ` Zhang, Qi Z
2021-09-24 11:08   ` [dpdk-stable] [PATCH v2 0/2] i40e Rx descriptor loads ordering Zhang, Qi Z

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