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From: Ruifeng Wang <ruifeng.wang@arm.com>
To: dev@dpdk.org
Cc: beilei.xing@intel.com, qi.z.zhang@intel.com,
	bruce.richardson@intel.com, jerinj@marvell.com,
	hemant.agrawal@nxp.com, drc@linux.vnet.ibm.com,
	honnappa.nagarahalli@arm.com, stable@dpdk.org, nd@arm.com,
	Ruifeng Wang <ruifeng.wang@arm.com>
Subject: [dpdk-stable] [PATCH 2/2] net/i40e: fix risk in Rx descriptor read in scalar path
Date: Mon,  6 Sep 2021 11:32:01 +0800
Message-ID: <20210906033201.1789796-3-ruifeng.wang@arm.com> (raw)
In-Reply-To: <20210906033201.1789796-1-ruifeng.wang@arm.com>

Rx descriptor is 16B/32B in size and consists of multiple words.
The word that includes DD field should be read first. Read result
with DD bit set indicates the rest part in a descriptor is valid.

In functions for simple Rx, the descriptor is not read atomically
in whole. On weaker ordered systems like aarch64, read of the word
that includes DD field could be reordered after read of other words.
In this case, some words could be invalid data.

Read barrier is inserted between read of the word with DD field
and read of other words. The barrier ensures what fetched is correct
descriptor data.

Fixes: 7b0cf70135d1 ("net/i40e: support ARM platform")
Cc: stable@dpdk.org

Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
---
The change should not impact performance on x86 as acquire fence is
ignored on x86.

 drivers/net/i40e/i40e_rxtx.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c
index 8329cbdd4e..c4cd6b6b60 100644
--- a/drivers/net/i40e/i40e_rxtx.c
+++ b/drivers/net/i40e/i40e_rxtx.c
@@ -746,6 +746,12 @@ i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 			break;
 		}
 
+		/**
+		 * Use acquire fence to ensure that qword1 which includes DD
+		 * bit is loaded before loading of other descriptor words.
+		 */
+		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+
 		rxd = *rxdp;
 		nb_hold++;
 		rxe = &sw_ring[rx_id];
@@ -862,6 +868,12 @@ i40e_recv_scattered_pkts(void *rx_queue,
 			break;
 		}
 
+		/**
+		 * Use acquire fence to ensure that qword1 which includes DD
+		 * bit is loaded before loading of other descriptor words.
+		 */
+		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+
 		rxd = *rxdp;
 		nb_hold++;
 		rxe = &sw_ring[rx_id];
-- 
2.25.1


  parent reply	other threads:[~2021-09-06  3:32 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-06  3:31 [dpdk-stable] [PATCH 0/2] i40e Rx descriptor loads ordering Ruifeng Wang
2021-09-06  3:32 ` [dpdk-stable] [PATCH 1/2] net/i40e: fix risk in Rx descriptor read in NEON vector path Ruifeng Wang
2021-09-14 18:33   ` Honnappa Nagarahalli
2021-09-15  8:42     ` Ruifeng Wang
2021-09-06  3:32 ` Ruifeng Wang [this message]
2021-09-14 18:06   ` [dpdk-stable] [PATCH 2/2] net/i40e: fix risk in Rx descriptor read in scalar path Honnappa Nagarahalli
2021-09-15  8:33 ` [dpdk-stable] [PATCH v2 0/2] i40e Rx descriptor loads ordering Ruifeng Wang
2021-09-15  8:33   ` [dpdk-stable] [PATCH v2 1/2] net/i40e: fix risk in Rx descriptor read in NEON vector path Ruifeng Wang
2021-09-15  8:33   ` [dpdk-stable] [PATCH v2 2/2] net/i40e: fix risk in Rx descriptor read in scalar path Ruifeng Wang
2021-09-29 15:05     ` Ferruh Yigit
2021-09-29 15:29       ` Honnappa Nagarahalli
2021-10-11 16:26         ` Ferruh Yigit
2021-10-19 11:14           ` Zhang, Qi Z
2021-11-05  6:57             ` Ruifeng Wang
2021-11-11 10:27               ` Ruifeng Wang
2021-11-11 12:27     ` Zhang, Qi Z
2021-09-24 11:08   ` [dpdk-stable] [PATCH v2 0/2] i40e Rx descriptor loads ordering Zhang, Qi Z

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