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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.32 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.32; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.32) by BN8NAM11FT005.mail.protection.outlook.com (10.13.176.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4544.13 via Frontend Transport; Mon, 27 Sep 2021 08:02:21 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 27 Sep 2021 01:02:20 -0700 Received: from nvidia.com (172.20.187.5) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 27 Sep 2021 08:02:18 +0000 From: Bing Zhao To: , CC: , , , Date: Mon, 27 Sep 2021 11:02:03 +0300 Message-ID: <20210927080203.23877-1-bingz@nvidia.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a3b2f212-9aff-4f24-9d89-08d9818d227f X-MS-TrafficTypeDiagnostic: BY5PR12MB3651: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(508600001)(70206006)(70586007)(83380400001)(4326008)(36756003)(26005)(107886003)(186003)(1076003)(7636003)(8936002)(336012)(450100002)(6636002)(356005)(54906003)(36860700001)(7696005)(16526019)(47076005)(86362001)(2616005)(8676002)(5660300002)(6286002)(2906002)(55016002)(6666004)(316002)(82310400003)(110136005)(426003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2021 08:02:21.7087 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a3b2f212-9aff-4f24-9d89-08d9818d227f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.32]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3651 Subject: [dpdk-stable] [PATCH] net/mlx5: fix Tx metadata endianness in data path X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" The metadata can be set in the mbuf dynamic field and then used in flow rules steering for egress direction. The hardware requires network order for both the insertion of a rule and sending a packet. Indeed, there is no strict restriction for the endianness. The order for sending a packet and its steering rule should be consistent. In the past, there was no endianness conversion due to the performance reason. The flow rule converted the metadata into little endian for hardware (if needed) and the packet hit the flow rule also with little endian. After the metadata was converted to big endian, the missing adaption in the data path resulted in a flow miss of the egress packets. Converting the metadata to big endian before posting a WQE to the hardware solves this issue. Fixes: b57e414b48c0 ("net/mlx5: convert meta register to big-endian") Cc: akozyrev@nvidia.com Cc: stable@dpdk.org Signed-off-by: Bing Zhao Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_tx.h | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h index 1a35919371..77d6069755 100644 --- a/drivers/net/mlx5/mlx5_tx.h +++ b/drivers/net/mlx5/mlx5_tx.h @@ -953,7 +953,8 @@ mlx5_tx_eseg_none(struct mlx5_txq_data *__rte_restrict txq __rte_unused, /* Fill metadata field if needed. */ es->metadata = MLX5_TXOFF_CONFIG(METADATA) ? loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ? - *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0; + rte_cpu_to_be_32(*RTE_FLOW_DYNF_METADATA(loc->mbuf)) : + 0 : 0; /* Engage VLAN tag insertion feature if requested. */ if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) { @@ -1013,7 +1014,8 @@ mlx5_tx_eseg_dmin(struct mlx5_txq_data *__rte_restrict txq __rte_unused, /* Fill metadata field if needed. */ es->metadata = MLX5_TXOFF_CONFIG(METADATA) ? loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ? - *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0; + rte_cpu_to_be_32(*RTE_FLOW_DYNF_METADATA(loc->mbuf)) : + 0 : 0; psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *); es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE); es->inline_data = *(unaligned_uint16_t *)psrc; @@ -1096,7 +1098,8 @@ mlx5_tx_eseg_data(struct mlx5_txq_data *__rte_restrict txq, /* Fill metadata field if needed. */ es->metadata = MLX5_TXOFF_CONFIG(METADATA) ? loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ? - *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0; + rte_cpu_to_be_32(*RTE_FLOW_DYNF_METADATA(loc->mbuf)) : + 0 : 0; psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *); es->inline_hdr_sz = rte_cpu_to_be_16(inlen); es->inline_data = *(unaligned_uint16_t *)psrc; @@ -1308,7 +1311,8 @@ mlx5_tx_eseg_mdat(struct mlx5_txq_data *__rte_restrict txq, /* Fill metadata field if needed. */ es->metadata = MLX5_TXOFF_CONFIG(METADATA) ? loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ? - *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0; + rte_cpu_to_be_32(*RTE_FLOW_DYNF_METADATA(loc->mbuf)) : + 0 : 0; MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE); pdst = (uint8_t *)&es->inline_data; if (MLX5_TXOFF_CONFIG(VLAN) && vlan) { @@ -2470,7 +2474,7 @@ mlx5_tx_match_empw(struct mlx5_txq_data *__rte_restrict txq, /* Fill metadata field if needed. */ if (MLX5_TXOFF_CONFIG(METADATA) && es->metadata != (loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ? - *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0)) + rte_cpu_to_be_32(*RTE_FLOW_DYNF_METADATA(loc->mbuf)) : 0)) return false; /* Legacy MPW can send packets with the same length only. */ if (MLX5_TXOFF_CONFIG(MPW) && -- 2.27.0