* [dpdk-stable] [PATCH v2 01/13] net/mlx5: fix software parsing support query
[not found] <20211012124554.21296-1-talshn@nvidia.com>
@ 2021-10-12 12:45 ` Tal Shnaiderman
2021-10-12 12:45 ` [dpdk-stable] [PATCH v2 04/13] net/mlx5: fix tunneling " Tal Shnaiderman
1 sibling, 0 replies; 2+ messages in thread
From: Tal Shnaiderman @ 2021-10-12 12:45 UTC (permalink / raw)
To: dev
Cc: thomas, matan, rasland, asafp, viacheslavo, eilong, kcollins,
idanhac, stable
Currently, the PMD decides if the software parsing
offload can enable outer IPv4 checksum and tunneled
TSO support by checking config->hw_csum and config->tso
respectively.
This is incorrect, the right way is to check the following
flags returned by the mlx5dv_query_device function:
MLX5DV_SW_PARSING - check general swp support.
MLX5DV_SW_PARSING_CSUM - check swp checksum support.
MLX5DV_SW_PARSING_LSO - check swp LSO/TSO support.
The fix enables the offloads according to the correct
flags returned by the kernel.
Fixes: e46821e9fcdc60 ("net/mlx5: separate generic tunnel TSO from the standard one")
Cc: stable@dpdk.org
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Tested-by: Idan Hackmon <idanhac@nvidia.com>
---
drivers/net/mlx5/linux/mlx5_os.c | 3 ++-
drivers/net/mlx5/linux/mlx5_os.h | 12 ++++++++++++
drivers/net/mlx5/mlx5.h | 2 +-
drivers/net/mlx5/mlx5_txq.c | 15 +++++++++------
4 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index 3746057673..a6542629c7 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -1112,7 +1112,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
DRV_LOG(DEBUG, "SWP support: %u", swp);
#endif
- config->swp = !!swp;
+ config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
+ MLX5_SW_PARSING_TSO_CAP);
#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
struct mlx5dv_striding_rq_caps mprq_caps =
diff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h
index 2991d37df2..da036edb72 100644
--- a/drivers/net/mlx5/linux/mlx5_os.h
+++ b/drivers/net/mlx5/linux/mlx5_os.h
@@ -21,4 +21,16 @@ enum {
int mlx5_auxiliary_get_ifindex(const char *sf_name);
+
+enum mlx5_sw_parsing_offloads {
+#ifdef HAVE_IBV_MLX5_MOD_SWP
+ MLX5_SW_PARSING_CAP = MLX5DV_SW_PARSING,
+ MLX5_SW_PARSING_CSUM_CAP = MLX5DV_SW_PARSING_CSUM,
+ MLX5_SW_PARSING_TSO_CAP = MLX5DV_SW_PARSING_LSO,
+#else
+ MLX5_SW_PARSING_CAP = 0,
+ MLX5_SW_PARSING_CSUM_CAP = 0,
+ MLX5_SW_PARSING_TSO_CAP = 0,
+#endif
+};
#endif /* RTE_PMD_MLX5_OS_H_ */
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 3581414b78..edb4f26d42 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -260,7 +260,7 @@ struct mlx5_dev_config {
unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
unsigned int lacp_by_user:1;
/* Enable user to manage LACP traffic. */
- unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
+ unsigned int swp:3; /* Tx generic tunnel checksum and TSO offload. */
unsigned int devx:1; /* Whether devx interface is available or not. */
unsigned int dest_tir:1; /* Whether advanced DR API is available. */
unsigned int reclaim_mode:2; /* Memory reclaim mode. */
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index eb4d34ca55..8dca2b7f79 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -111,9 +111,9 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
if (config->tx_pp)
offloads |= DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP;
if (config->swp) {
- if (config->hw_csum)
+ if (config->swp & MLX5_SW_PARSING_CSUM_CAP)
offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
- if (config->tso)
+ if (config->swp & MLX5_SW_PARSING_TSO_CAP)
offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
DEV_TX_OFFLOAD_UDP_TNL_TSO);
}
@@ -979,10 +979,13 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
txq_ctrl->txq.tso_en = 1;
}
txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
- txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
- DEV_TX_OFFLOAD_UDP_TNL_TSO |
- DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
- txq_ctrl->txq.offloads) && config->swp;
+ txq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO |
+ DEV_TX_OFFLOAD_UDP_TNL_TSO) &
+ txq_ctrl->txq.offloads) && (config->swp &
+ MLX5_SW_PARSING_TSO_CAP)) |
+ ((DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM &
+ txq_ctrl->txq.offloads) && (config->swp &
+ MLX5_SW_PARSING_CSUM_CAP));
}
/**
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 2+ messages in thread* [dpdk-stable] [PATCH v2 04/13] net/mlx5: fix tunneling support query
[not found] <20211012124554.21296-1-talshn@nvidia.com>
2021-10-12 12:45 ` [dpdk-stable] [PATCH v2 01/13] net/mlx5: fix software parsing support query Tal Shnaiderman
@ 2021-10-12 12:45 ` Tal Shnaiderman
1 sibling, 0 replies; 2+ messages in thread
From: Tal Shnaiderman @ 2021-10-12 12:45 UTC (permalink / raw)
To: dev
Cc: thomas, matan, rasland, asafp, viacheslavo, eilong, kcollins,
idanhac, stable
Currently, the PMD decides if the tunneling offload
can enable VXLAN/GRE/GENEVE tunneled TSO support by checking
config->tunnel_en (single bit) and config->tso.
This is incorrect, the right way is to check the following
flags returned by the mlx5dv_query_device function:
MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN - if supported the offload
DEV_TX_OFFLOAD_VXLAN_TNL_TSO can be enabled.
MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE - if supported the offload
DEV_TX_OFFLOAD_GRE_TNL_TSO can be enabled.
MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE - if supported the offload
DEV_TX_OFFLOAD_GENEVE_TNL_TSO can be enabled.
The fix enables the offloads according to the correct
flags returned by the kernel.
Fixes: dbccb4cddcd2f7c ("net/mlx5: convert to new Tx offloads API")
Cc: stable@dpdk.org
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Tested-by: Idan Hackmon <idanhac@nvidia.com>
---
drivers/net/mlx5/linux/mlx5_os.c | 28 +++++++++++++++++-----------
drivers/net/mlx5/linux/mlx5_os.h | 15 +++++++++++++++
drivers/net/mlx5/mlx5.h | 2 +-
drivers/net/mlx5/mlx5_txq.c | 24 +++++++++++++++++++-----
drivers/net/mlx5/windows/mlx5_os.h | 6 ++++++
5 files changed, 58 insertions(+), 17 deletions(-)
diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index a6542629c7..9ac354fabe 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -963,7 +963,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
int err = 0;
unsigned int hw_padding = 0;
unsigned int mps;
- unsigned int tunnel_en = 0;
unsigned int mpls_en = 0;
unsigned int swp = 0;
unsigned int mprq = 0;
@@ -1145,20 +1144,27 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
config->cqe_comp = 1;
#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
- tunnel_en = ((dv_attr.tunnel_offloads_caps &
- MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
- (dv_attr.tunnel_offloads_caps &
- MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
- (dv_attr.tunnel_offloads_caps &
- MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
- }
- DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
- tunnel_en ? "" : "not ");
+ config->tunnel_en = dv_attr.tunnel_offloads_caps &
+ (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN |
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE |
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE);
+ }
+ if (config->tunnel_en) {
+ DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
+ config->tunnel_en &
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN ? "[VXLAN]" : "",
+ config->tunnel_en &
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE ? "[GRE]" : "",
+ config->tunnel_en &
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE ? "[GENEVE]" : ""
+ );
+ } else {
+ DRV_LOG(DEBUG, "tunnel offloading is not supported");
+ }
#else
DRV_LOG(WARNING,
"tunnel offloading disabled due to old OFED/rdma-core version");
#endif
- config->tunnel_en = tunnel_en;
#ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
mpls_en = ((dv_attr.tunnel_offloads_caps &
MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
diff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h
index da036edb72..80c70d713a 100644
--- a/drivers/net/mlx5/linux/mlx5_os.h
+++ b/drivers/net/mlx5/linux/mlx5_os.h
@@ -33,4 +33,19 @@ enum mlx5_sw_parsing_offloads {
MLX5_SW_PARSING_TSO_CAP = 0,
#endif
};
+
+enum mlx5_tunnel_offloads {
+#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
+ MLX5_TUNNELED_OFFLOADS_VXLAN_CAP =
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN,
+ MLX5_TUNNELED_OFFLOADS_GRE_CAP =
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE,
+ MLX5_TUNNELED_OFFLOADS_GENEVE_CAP =
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE,
+#else
+ MLX5_TUNNELED_OFFLOADS_VXLAN_CAP = 0,
+ MLX5_TUNNELED_OFFLOADS_GRE_CAP = 0,
+ MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 0,
+#endif
+};
#endif /* RTE_PMD_MLX5_OS_H_ */
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 0694927457..58f12cd75c 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -244,7 +244,7 @@ struct mlx5_dev_config {
unsigned int hw_padding:1; /* End alignment padding is supported. */
unsigned int vf:1; /* This is a VF. */
unsigned int sf:1; /* This is a SF. */
- unsigned int tunnel_en:1;
+ unsigned int tunnel_en:3;
/* Whether tunnel stateless offloads are supported. */
unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
unsigned int cqe_comp:1; /* CQE compression is enabled. */
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 8dca2b7f79..54f42292ac 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -120,10 +120,17 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
if (config->tunnel_en) {
if (config->hw_csum)
offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
- if (config->tso)
- offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
- DEV_TX_OFFLOAD_GRE_TNL_TSO |
- DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
+ if (config->tso) {
+ if (config->tunnel_en &
+ MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)
+ offloads |= DEV_TX_OFFLOAD_VXLAN_TNL_TSO;
+ if (config->tunnel_en &
+ MLX5_TUNNELED_OFFLOADS_GRE_CAP)
+ offloads |= DEV_TX_OFFLOAD_GRE_TNL_TSO;
+ if (config->tunnel_en &
+ MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)
+ offloads |= DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
+ }
}
if (!config->mprq.enabled)
offloads |= DEV_TX_OFFLOAD_MBUF_FAST_FREE;
@@ -978,7 +985,14 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
MLX5_MAX_TSO_HEADER);
txq_ctrl->txq.tso_en = 1;
}
- txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
+ if (((DEV_TX_OFFLOAD_VXLAN_TNL_TSO & txq_ctrl->txq.offloads) &&
+ (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)) |
+ ((DEV_TX_OFFLOAD_GRE_TNL_TSO & txq_ctrl->txq.offloads) &&
+ (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GRE_CAP)) |
+ ((DEV_TX_OFFLOAD_GENEVE_TNL_TSO & txq_ctrl->txq.offloads) &&
+ (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)) |
+ (config->swp & MLX5_SW_PARSING_TSO_CAP))
+ txq_ctrl->txq.tunnel_en = 1;
txq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO |
DEV_TX_OFFLOAD_UDP_TNL_TSO) &
txq_ctrl->txq.offloads) && (config->swp &
diff --git a/drivers/net/mlx5/windows/mlx5_os.h b/drivers/net/mlx5/windows/mlx5_os.h
index 6de683357c..8b58265687 100644
--- a/drivers/net/mlx5/windows/mlx5_os.h
+++ b/drivers/net/mlx5/windows/mlx5_os.h
@@ -22,4 +22,10 @@ enum mlx5_sw_parsing_offloads {
MLX5_SW_PARSING_TSO_CAP = 1 << 2,
};
+enum mlx5_tunnel_offloads {
+ MLX5_TUNNELED_OFFLOADS_VXLAN_CAP = 1 << 0,
+ MLX5_TUNNELED_OFFLOADS_GRE_CAP = 1 << 1,
+ MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 1 << 2,
+};
+
#endif /* RTE_PMD_MLX5_OS_H_ */
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 2+ messages in thread