From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2E747A0C47 for ; Tue, 12 Oct 2021 14:46:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1F9D1411A2; Tue, 12 Oct 2021 14:46:46 +0200 (CEST) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2083.outbound.protection.outlook.com [40.107.93.83]) by mails.dpdk.org (Postfix) with ESMTP id 6B4624117E; Tue, 12 Oct 2021 14:46:41 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=eJuDcb2GEk7ik/bwzJ54ULfa4x0ZuEw68aRHWit0ntJLsp+YHs+J8G6ZCcZfYWwekq5XosGkzgwW/mFxwcMZgXFFRuJaHwzsplebGFXPFWBSI+BqsRGx+tBpF1+ZwTMa7Ej2wIggq7O3mGDjZirvALZ1us9dc5arW3l0ExEqNSU6QMWaG0dRr9VyHPrPhFApFvFcsY0RcxZJNDdhLsJj4icsL4p1K7d7x28MdiTzvpPTjqEtuW5zQkK867usIFInc8F4UhaGdoXPObI3NiS76TEoxGJmR2IzJKYolskHB7C0T9htbZMG5M285qWa3V/HKGpPniVws2zmbsmgbPH22g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=X6oaoVCzK5ccNEcAlXQCWTj168vlbTXsRoDbeG+vzHg=; b=cjfHXGjTmOaTPsGVu4GggL88d2DO8+qmHfcwJUGI7UG7LbIAwhzwGeVwgPFNoeTmNkbo5SU9DEDiGy6Ej0IW9DCrIwnUUk06NiT7qNoi7xHL733roxjNN1gpOkagBYv/awNhzaL+c7omjjzSlHvQTM0+t8ysIjj0QnaNEi06sXmzdVTXsHTjLu7yvYXks/DniUx0hRRl9SopLbu+uLOyndzLZRf3VIWLQZDy0LsTDy85vCSo+02YC/48wo+AVGmVf+40geKYtB0NxVlOAOn1320+wZFyeSjS+j4mAReyc7PlRowk6l34WdTzOEgul3UyP3dlcHnI9GoBEa5fkclfSA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=X6oaoVCzK5ccNEcAlXQCWTj168vlbTXsRoDbeG+vzHg=; b=GYfrDngJkj3VpDJfmRh1ysbaiFl69TV7IU81dU789GfU9QLuMxZaaRw+KI1BFpwOEtGUAZPPmYtl2TVtN3dD7K4+R/9p4cRiS6sKcAOfWIsD1lb1QsnLGeHvt1uIcglLpyu4nn6/X8/Hu8d+lWTfXKhr0f9BEgqFk5D2F1kAWTDpsqBhrNx+mO+RZyCMOn5M33PebFc12504tYR6yqGCe00NEXtTtkt87K45d/kKK+nluagF7HaA+WWTuEdt28D30BSk1/wNYncTE2eb8uNuv5wNq6/ZUp0hudcOOA/cpMN2X8/UIMKxFsiyrnDPrcoV2n+FjA4dXQM05xeKrn8HvQ== Received: from DM6PR02CA0139.namprd02.prod.outlook.com (2603:10b6:5:332::6) by DM6PR12MB2891.namprd12.prod.outlook.com (2603:10b6:5:188::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.22; Tue, 12 Oct 2021 12:46:39 +0000 Received: from DM6NAM11FT008.eop-nam11.prod.protection.outlook.com (2603:10b6:5:332:cafe::cb) by DM6PR02CA0139.outlook.office365.com (2603:10b6:5:332::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.14 via Frontend Transport; Tue, 12 Oct 2021 12:46:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT008.mail.protection.outlook.com (10.13.172.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4587.18 via Frontend Transport; Tue, 12 Oct 2021 12:46:39 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 12 Oct 2021 12:46:30 +0000 From: Tal Shnaiderman To: CC: , , , , , , , , Date: Tue, 12 Oct 2021 15:45:45 +0300 Message-ID: <20211012124554.21296-5-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20211012124554.21296-1-talshn@nvidia.com> References: <20211012124554.21296-1-talshn@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ff341efe-7ba7-40e3-e90b-08d98d7e560d X-MS-TrafficTypeDiagnostic: DM6PR12MB2891: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1169; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: G6J5gGu6AonECBaQ5v7LqPk7JWsFeWCXI3U01fIV1gAFHrjoFGIlDtkNtBpbEHMz0cHRJfeTg9wFZQsfPcoC/LeFVzLryAP21aLcoz7vvImb3arT7VxYT0gPsoMjOOK9REkxMSV30Yw3FysogXgSBSNWSk1gz7g/4BcT15z7gzuIsECUMKPilnc2iuetSqFGyXxVF21yMOtNSJ3jHCK4j4ibFILgiRRmE9B2xv9NANGMeavK81fgwlkM46j4bDX4GTERTZF0P7SoKYhwErDcdXQSBuc0wgL9rxufM23laWxeuTYf07We++wBWl5D9bqb/LD1LNmgpS640rhLPqrRTebJDf2UHMZPQqhvhcoOacbBL3FbgvaaBtK+4IMFNcMSjcv42Cs8bt2ABEj8rvw3/Q3j6MEBxabe8gVtaHdOX6IQOL+4XYBroYdKvZ/bcupqFJJRivp8jC/gHI7Ef+W6riOybBzjR8YhzM7ZJjfLyomHF2D9F7dxY2Z+p6bsveC/aqb57BpK44Va7xq0NTFugqU361JvXWlyPMPUxN1Whyh0GgvBoEUM7g7lfJcTPazxA7YnC1CYuGMPZAAyeHWWQ+QaRvJAQ0JRA8nVR5KOcegaSX2k/H6EYo7wiWZP3JPad/dDebeF2RNHgSXb0MOCwkniqZjb3bFASrgDw5WdiHpzYOjwqMynX44mAGK0fRWfYYps2wBPVwCls6WH/vUBqw== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(6916009)(70586007)(70206006)(356005)(6286002)(47076005)(36906005)(6666004)(2906002)(508600001)(2616005)(86362001)(7696005)(8676002)(1076003)(316002)(5660300002)(36756003)(8936002)(426003)(336012)(4326008)(82310400003)(16526019)(186003)(54906003)(36860700001)(83380400001)(7636003)(55016002)(26005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Oct 2021 12:46:39.7585 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff341efe-7ba7-40e3-e90b-08d98d7e560d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2891 Subject: [dpdk-stable] [PATCH v2 04/13] net/mlx5: fix tunneling support query X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Currently, the PMD decides if the tunneling offload can enable VXLAN/GRE/GENEVE tunneled TSO support by checking config->tunnel_en (single bit) and config->tso. This is incorrect, the right way is to check the following flags returned by the mlx5dv_query_device function: MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN - if supported the offload DEV_TX_OFFLOAD_VXLAN_TNL_TSO can be enabled. MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE - if supported the offload DEV_TX_OFFLOAD_GRE_TNL_TSO can be enabled. MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE - if supported the offload DEV_TX_OFFLOAD_GENEVE_TNL_TSO can be enabled. The fix enables the offloads according to the correct flags returned by the kernel. Fixes: dbccb4cddcd2f7c ("net/mlx5: convert to new Tx offloads API") Cc: stable@dpdk.org Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad Tested-by: Idan Hackmon --- drivers/net/mlx5/linux/mlx5_os.c | 28 +++++++++++++++++----------- drivers/net/mlx5/linux/mlx5_os.h | 15 +++++++++++++++ drivers/net/mlx5/mlx5.h | 2 +- drivers/net/mlx5/mlx5_txq.c | 24 +++++++++++++++++++----- drivers/net/mlx5/windows/mlx5_os.h | 6 ++++++ 5 files changed, 58 insertions(+), 17 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index a6542629c7..9ac354fabe 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -963,7 +963,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, int err = 0; unsigned int hw_padding = 0; unsigned int mps; - unsigned int tunnel_en = 0; unsigned int mpls_en = 0; unsigned int swp = 0; unsigned int mprq = 0; @@ -1145,20 +1144,27 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, config->cqe_comp = 1; #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { - tunnel_en = ((dv_attr.tunnel_offloads_caps & - MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && - (dv_attr.tunnel_offloads_caps & - MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && - (dv_attr.tunnel_offloads_caps & - MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); - } - DRV_LOG(DEBUG, "tunnel offloading is %ssupported", - tunnel_en ? "" : "not "); + config->tunnel_en = dv_attr.tunnel_offloads_caps & + (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN | + MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE | + MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE); + } + if (config->tunnel_en) { + DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s", + config->tunnel_en & + MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN ? "[VXLAN]" : "", + config->tunnel_en & + MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE ? "[GRE]" : "", + config->tunnel_en & + MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE ? "[GENEVE]" : "" + ); + } else { + DRV_LOG(DEBUG, "tunnel offloading is not supported"); + } #else DRV_LOG(WARNING, "tunnel offloading disabled due to old OFED/rdma-core version"); #endif - config->tunnel_en = tunnel_en; #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT mpls_en = ((dv_attr.tunnel_offloads_caps & MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && diff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h index da036edb72..80c70d713a 100644 --- a/drivers/net/mlx5/linux/mlx5_os.h +++ b/drivers/net/mlx5/linux/mlx5_os.h @@ -33,4 +33,19 @@ enum mlx5_sw_parsing_offloads { MLX5_SW_PARSING_TSO_CAP = 0, #endif }; + +enum mlx5_tunnel_offloads { +#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT + MLX5_TUNNELED_OFFLOADS_VXLAN_CAP = + MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN, + MLX5_TUNNELED_OFFLOADS_GRE_CAP = + MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE, + MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = + MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE, +#else + MLX5_TUNNELED_OFFLOADS_VXLAN_CAP = 0, + MLX5_TUNNELED_OFFLOADS_GRE_CAP = 0, + MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 0, +#endif +}; #endif /* RTE_PMD_MLX5_OS_H_ */ diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 0694927457..58f12cd75c 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -244,7 +244,7 @@ struct mlx5_dev_config { unsigned int hw_padding:1; /* End alignment padding is supported. */ unsigned int vf:1; /* This is a VF. */ unsigned int sf:1; /* This is a SF. */ - unsigned int tunnel_en:1; + unsigned int tunnel_en:3; /* Whether tunnel stateless offloads are supported. */ unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ unsigned int cqe_comp:1; /* CQE compression is enabled. */ diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index 8dca2b7f79..54f42292ac 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -120,10 +120,17 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev) if (config->tunnel_en) { if (config->hw_csum) offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; - if (config->tso) - offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO | - DEV_TX_OFFLOAD_GRE_TNL_TSO | - DEV_TX_OFFLOAD_GENEVE_TNL_TSO); + if (config->tso) { + if (config->tunnel_en & + MLX5_TUNNELED_OFFLOADS_VXLAN_CAP) + offloads |= DEV_TX_OFFLOAD_VXLAN_TNL_TSO; + if (config->tunnel_en & + MLX5_TUNNELED_OFFLOADS_GRE_CAP) + offloads |= DEV_TX_OFFLOAD_GRE_TNL_TSO; + if (config->tunnel_en & + MLX5_TUNNELED_OFFLOADS_GENEVE_CAP) + offloads |= DEV_TX_OFFLOAD_GENEVE_TNL_TSO; + } } if (!config->mprq.enabled) offloads |= DEV_TX_OFFLOAD_MBUF_FAST_FREE; @@ -978,7 +985,14 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl) MLX5_MAX_TSO_HEADER); txq_ctrl->txq.tso_en = 1; } - txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp; + if (((DEV_TX_OFFLOAD_VXLAN_TNL_TSO & txq_ctrl->txq.offloads) && + (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)) | + ((DEV_TX_OFFLOAD_GRE_TNL_TSO & txq_ctrl->txq.offloads) && + (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GRE_CAP)) | + ((DEV_TX_OFFLOAD_GENEVE_TNL_TSO & txq_ctrl->txq.offloads) && + (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)) | + (config->swp & MLX5_SW_PARSING_TSO_CAP)) + txq_ctrl->txq.tunnel_en = 1; txq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO | DEV_TX_OFFLOAD_UDP_TNL_TSO) & txq_ctrl->txq.offloads) && (config->swp & diff --git a/drivers/net/mlx5/windows/mlx5_os.h b/drivers/net/mlx5/windows/mlx5_os.h index 6de683357c..8b58265687 100644 --- a/drivers/net/mlx5/windows/mlx5_os.h +++ b/drivers/net/mlx5/windows/mlx5_os.h @@ -22,4 +22,10 @@ enum mlx5_sw_parsing_offloads { MLX5_SW_PARSING_TSO_CAP = 1 << 2, }; +enum mlx5_tunnel_offloads { + MLX5_TUNNELED_OFFLOADS_VXLAN_CAP = 1 << 0, + MLX5_TUNNELED_OFFLOADS_GRE_CAP = 1 << 1, + MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 1 << 2, +}; + #endif /* RTE_PMD_MLX5_OS_H_ */ -- 2.16.1.windows.4