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intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT021.mail.protection.outlook.com (10.13.173.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4690.15 via Frontend Transport; Wed, 10 Nov 2021 06:44:13 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 10 Nov 2021 06:44:12 +0000 From: Xueming Li To: Yunjian Wang CC: Luca Boccassi , Haiyue Wang , dpdk stable Date: Wed, 10 Nov 2021 14:29:53 +0800 Message-ID: <20211110063216.2744012-110-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211110063216.2744012-1-xuemingl@nvidia.com> References: <20211110063216.2744012-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5d63254c-e7c7-4f6d-7b0d-08d9a415828c X-MS-TrafficTypeDiagnostic: CH2PR12MB4231: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(6286002)(47076005)(26005)(8936002)(16526019)(426003)(54906003)(1076003)(83380400001)(36860700001)(356005)(55016002)(7636003)(8676002)(7696005)(36756003)(5660300002)(6666004)(6916009)(40140700001)(186003)(2616005)(316002)(508600001)(4001150100001)(86362001)(53546011)(966005)(4326008)(82310400003)(2906002)(336012)(70586007)(70206006)(36906005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2021 06:44:13.9929 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d63254c-e7c7-4f6d-7b0d-08d9a415828c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4231 Subject: [dpdk-stable] patch 'net/i40e: fix memzone leak on queue re-configure' has been queued to stable release 20.11.4 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 20.11.4 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/12/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/4e60a45559807ed5b18caca0006f03c335f3b538 Thanks. Xueming Li --- >From 4e60a45559807ed5b18caca0006f03c335f3b538 Mon Sep 17 00:00:00 2001 From: Yunjian Wang Date: Wed, 22 Sep 2021 21:29:36 +0800 Subject: [PATCH] net/i40e: fix memzone leak on queue re-configure Cc: Xueming Li [ upstream commit e3188d5f9925d378be535bb48ccb5f26834605aa ] Normally when closing the device the queue memzone should be freed. But the memzone will be not freed, when device setup ops like: rte_eth_bond_slave_remove -->__eth_bond_slave_remove_lock_free ---->slave_remove ------>rte_eth_dev_internal_reset -------->rte_eth_dev_rx_queue_config ---------->eth_dev_rx_queue_config ------------>i40e_dev_rx_queue_release rte_eth_dev_close -->i40e_dev_close ---->i40e_dev_free_queues ------>i40e_dev_rx_queue_release (not been called due to nb_rx_queues and nb_tx_queues are 0) And when queue number is changed to small size, the BIG memzone queue index will be lost. This will lead to a memory leak. So we should release the memzone when releasing queues. Fixes: 460d1679586e ("drivers/net: delete HW rings while freeing queues") Signed-off-by: Yunjian Wang Acked-by: Haiyue Wang --- drivers/net/i40e/i40e_fdir.c | 3 --- drivers/net/i40e/i40e_rxtx.c | 8 ++++++-- drivers/net/i40e/i40e_rxtx.h | 2 ++ 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c index 05fdcef24f..6af71ed23d 100644 --- a/drivers/net/i40e/i40e_fdir.c +++ b/drivers/net/i40e/i40e_fdir.c @@ -283,7 +283,6 @@ i40e_fdir_teardown(struct i40e_pf *pf) { struct i40e_hw *hw = I40E_PF_TO_HW(pf); struct i40e_vsi *vsi; - struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id]; vsi = pf->fdir.fdir_vsi; if (!vsi) @@ -300,10 +299,8 @@ i40e_fdir_teardown(struct i40e_pf *pf) if (err) PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off"); - rte_eth_dma_zone_free(dev, "fdir_rx_ring", pf->fdir.rxq->queue_id); i40e_dev_rx_queue_release(pf->fdir.rxq); pf->fdir.rxq = NULL; - rte_eth_dma_zone_free(dev, "fdir_tx_ring", pf->fdir.txq->queue_id); i40e_dev_tx_queue_release(pf->fdir.txq); pf->fdir.txq = NULL; i40e_vsi_release(vsi); diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index 154f649b45..d1659ef060 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -1932,6 +1932,7 @@ i40e_dev_rx_queue_setup(struct rte_eth_dev *dev, return -ENOMEM; } + rxq->mz = rz; /* Zero all the descriptors in the ring. */ memset(rz->addr, 0, ring_size); @@ -2011,6 +2012,7 @@ i40e_dev_rx_queue_release(void *rxq) i40e_rx_queue_release_mbufs(q); rte_free(q->sw_ring); + rte_memzone_free(q->mz); rte_free(q); } @@ -2331,6 +2333,7 @@ i40e_dev_tx_queue_setup(struct rte_eth_dev *dev, return -ENOMEM; } + txq->mz = tz; txq->nb_tx_desc = nb_desc; txq->tx_rs_thresh = tx_rs_thresh; txq->tx_free_thresh = tx_free_thresh; @@ -2404,6 +2407,7 @@ i40e_dev_tx_queue_release(void *txq) i40e_tx_queue_release_mbufs(q); rte_free(q->sw_ring); + rte_memzone_free(q->mz); rte_free(q); } @@ -2941,7 +2945,6 @@ i40e_dev_free_queues(struct rte_eth_dev *dev) continue; i40e_dev_rx_queue_release(dev->data->rx_queues[i]); dev->data->rx_queues[i] = NULL; - rte_eth_dma_zone_free(dev, "rx_ring", i); } for (i = 0; i < dev->data->nb_tx_queues; i++) { @@ -2949,7 +2952,6 @@ i40e_dev_free_queues(struct rte_eth_dev *dev) continue; i40e_dev_tx_queue_release(dev->data->tx_queues[i]); dev->data->tx_queues[i] = NULL; - rte_eth_dma_zone_free(dev, "tx_ring", i); } } @@ -2992,6 +2994,7 @@ i40e_fdir_setup_tx_resources(struct i40e_pf *pf) return I40E_ERR_NO_MEMORY; } + txq->mz = tz; txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC; txq->queue_id = I40E_FDIR_QUEUE_ID; txq->reg_idx = pf->fdir.fdir_vsi->base_queue; @@ -3050,6 +3053,7 @@ i40e_fdir_setup_rx_resources(struct i40e_pf *pf) return I40E_ERR_NO_MEMORY; } + rxq->mz = rz; rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC; rxq->queue_id = I40E_FDIR_QUEUE_ID; rxq->reg_idx = pf->fdir.fdir_vsi->base_queue; diff --git a/drivers/net/i40e/i40e_rxtx.h b/drivers/net/i40e/i40e_rxtx.h index 57d7b4160b..0671750779 100644 --- a/drivers/net/i40e/i40e_rxtx.h +++ b/drivers/net/i40e/i40e_rxtx.h @@ -121,6 +121,7 @@ struct i40e_rx_queue { uint16_t rx_using_sse; /** + +[ upstream commit e3188d5f9925d378be535bb48ccb5f26834605aa ] @@ -28 +30,0 @@ -Cc: stable@dpdk.org @@ -39 +41 @@ -index 105a6a657f..df2a5aaecc 100644 +index 05fdcef24f..6af71ed23d 100644 @@ -42 +44 @@ -@@ -284,7 +284,6 @@ i40e_fdir_teardown(struct i40e_pf *pf) +@@ -283,7 +283,6 @@ i40e_fdir_teardown(struct i40e_pf *pf) @@ -50 +52 @@ -@@ -301,10 +300,8 @@ i40e_fdir_teardown(struct i40e_pf *pf) +@@ -300,10 +299,8 @@ i40e_fdir_teardown(struct i40e_pf *pf) @@ -55 +57 @@ - i40e_rx_queue_release(pf->fdir.rxq); + i40e_dev_rx_queue_release(pf->fdir.rxq); @@ -58 +60 @@ - i40e_tx_queue_release(pf->fdir.txq); + i40e_dev_tx_queue_release(pf->fdir.txq); @@ -62 +64 @@ -index caab66e433..807e1a4133 100644 +index 154f649b45..d1659ef060 100644 @@ -65 +67 @@ -@@ -2024,6 +2024,7 @@ i40e_dev_rx_queue_setup(struct rte_eth_dev *dev, +@@ -1932,6 +1932,7 @@ i40e_dev_rx_queue_setup(struct rte_eth_dev *dev, @@ -73 +75 @@ -@@ -2115,6 +2116,7 @@ i40e_rx_queue_release(void *rxq) +@@ -2011,6 +2012,7 @@ i40e_dev_rx_queue_release(void *rxq) @@ -81 +83 @@ -@@ -2427,6 +2429,7 @@ i40e_dev_tx_queue_setup(struct rte_eth_dev *dev, +@@ -2331,6 +2333,7 @@ i40e_dev_tx_queue_setup(struct rte_eth_dev *dev, @@ -89 +91 @@ -@@ -2500,6 +2503,7 @@ i40e_tx_queue_release(void *txq) +@@ -2404,6 +2407,7 @@ i40e_dev_tx_queue_release(void *txq) @@ -97 +99 @@ -@@ -3056,7 +3060,6 @@ i40e_dev_free_queues(struct rte_eth_dev *dev) +@@ -2941,7 +2945,6 @@ i40e_dev_free_queues(struct rte_eth_dev *dev) @@ -99 +101 @@ - i40e_rx_queue_release(dev->data->rx_queues[i]); + i40e_dev_rx_queue_release(dev->data->rx_queues[i]); @@ -105 +107 @@ -@@ -3064,7 +3067,6 @@ i40e_dev_free_queues(struct rte_eth_dev *dev) +@@ -2949,7 +2952,6 @@ i40e_dev_free_queues(struct rte_eth_dev *dev) @@ -107 +109 @@ - i40e_tx_queue_release(dev->data->tx_queues[i]); + i40e_dev_tx_queue_release(dev->data->tx_queues[i]); @@ -113 +115 @@ -@@ -3107,6 +3109,7 @@ i40e_fdir_setup_tx_resources(struct i40e_pf *pf) +@@ -2992,6 +2994,7 @@ i40e_fdir_setup_tx_resources(struct i40e_pf *pf) @@ -121 +123 @@ -@@ -3165,6 +3168,7 @@ i40e_fdir_setup_rx_resources(struct i40e_pf *pf) +@@ -3050,6 +3053,7 @@ i40e_fdir_setup_rx_resources(struct i40e_pf *pf) @@ -130 +132 @@ -index 8d6ab16b4f..5a99da1d3e 100644 +index 57d7b4160b..0671750779 100644 @@ -141 +143 @@ -@@ -166,6 +167,7 @@ struct i40e_tx_queue { +@@ -162,6 +163,7 @@ struct i40e_tx_queue {