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huawei.com; dkim=none (message not signed) header.d=none;huawei.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT004.mail.protection.outlook.com (10.13.172.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Wed, 10 Nov 2021 07:01:11 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 10 Nov 2021 07:00:06 +0000 From: Xueming Li To: Huisong Li CC: Luca Boccassi , Min Hu , dpdk stable Date: Wed, 10 Nov 2021 14:32:14 +0800 Message-ID: <20211110063216.2744012-251-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211110063216.2744012-1-xuemingl@nvidia.com> References: <20211110063216.2744012-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 88126d01-40fe-475e-b203-08d9a417e12f X-MS-TrafficTypeDiagnostic: MW3PR12MB4506: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(86362001)(47076005)(6286002)(6666004)(8936002)(508600001)(966005)(2906002)(26005)(36756003)(336012)(4326008)(186003)(16526019)(7696005)(53546011)(82310400003)(8676002)(316002)(70586007)(2616005)(70206006)(4001150100001)(5660300002)(36860700001)(6916009)(356005)(55016002)(7636003)(54906003)(426003)(83380400001)(1076003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2021 07:01:11.7748 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 88126d01-40fe-475e-b203-08d9a417e12f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT004.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4506 Subject: [dpdk-stable] patch 'net/hns3: simplify queue DMA address arithmetic' has been queued to stable release 20.11.4 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 20.11.4 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/12/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/42ea17b50b17f1fc482cc98c078cff72329ca1e3 Thanks. Xueming Li --- >From 42ea17b50b17f1fc482cc98c078cff72329ca1e3 Mon Sep 17 00:00:00 2001 From: Huisong Li Date: Sat, 6 Nov 2021 09:42:58 +0800 Subject: [PATCH] net/hns3: simplify queue DMA address arithmetic Cc: Xueming Li [ upstream commit f658f415814add688ade5783200143d14eefc51a ] The patch obtains the upper 32 bits of the Rx/Tx queue DMA address in one step instead of two steps. Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations") Signed-off-by: Huisong Li Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_rxtx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 9bfa9eef8a..4ae7c1f00a 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -308,7 +308,7 @@ hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq) hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr); hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG, - (uint32_t)((dma_addr >> 31) >> 1)); + (uint32_t)(dma_addr >> 32)); hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG, hns3_buf_size2type(rx_buf_len)); @@ -323,7 +323,7 @@ hns3_init_tx_queue_hw(struct hns3_tx_queue *txq) hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr); hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG, - (uint32_t)((dma_addr >> 31) >> 1)); + (uint32_t)(dma_addr >> 32)); hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG, HNS3_CFG_DESC_NUM(txq->nb_tx_desc)); -- 2.33.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-11-10 14:17:12.879792101 +0800 +++ 0250-net-hns3-simplify-queue-DMA-address-arithmetic.patch 2021-11-10 14:17:02.094077597 +0800 @@ -1 +1 @@ -From f658f415814add688ade5783200143d14eefc51a Mon Sep 17 00:00:00 2001 +From 42ea17b50b17f1fc482cc98c078cff72329ca1e3 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit f658f415814add688ade5783200143d14eefc51a ] @@ -10 +12,0 @@ -Cc: stable@dpdk.org @@ -19 +21 @@ -index ceb98025f8..00af73c850 100644 +index 9bfa9eef8a..4ae7c1f00a 100644 @@ -22 +24 @@ -@@ -322,7 +322,7 @@ hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq) +@@ -308,7 +308,7 @@ hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq) @@ -31 +33 @@ -@@ -337,7 +337,7 @@ hns3_init_tx_queue_hw(struct hns3_tx_queue *txq) +@@ -323,7 +323,7 @@ hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)