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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT025.mail.protection.outlook.com (10.13.172.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4734.22 via Frontend Transport; Sun, 28 Nov 2021 14:55:58 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 28 Nov 2021 14:55:56 +0000 From: Xueming Li To: Viacheslav Ovsiienko CC: Luca Boccassi , dpdk stable Subject: patch 'doc: describe timestamp limitations for mlx5' has been queued to stable release 20.11.4 Date: Sun, 28 Nov 2021 22:53:15 +0800 Message-ID: <20211128145423.3974892-12-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211128145423.3974892-1-xuemingl@nvidia.com> References: <20211110063216.2744012-1-xuemingl@nvidia.com> <20211128145423.3974892-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ea887fce-a41e-4ff7-6682-08d9b27f2ff1 X-MS-TrafficTypeDiagnostic: CY4PR12MB1704: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(70586007)(36756003)(966005)(508600001)(6286002)(6636002)(70206006)(316002)(7636003)(2906002)(55016003)(6862004)(5660300002)(82310400004)(4001150100001)(36860700001)(8936002)(4326008)(336012)(1076003)(53546011)(2616005)(426003)(8676002)(186003)(86362001)(16526019)(356005)(54906003)(26005)(6666004)(47076005)(7696005)(83380400001)(37006003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2021 14:55:58.3526 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea887fce-a41e-4ff7-6682-08d9b27f2ff1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1704 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 20.11.4 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/30/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/fdb91c91e807780d48e50e3f6158f0173f48c28c Thanks. Xueming Li --- >From fdb91c91e807780d48e50e3f6158f0173f48c28c Mon Sep 17 00:00:00 2001 From: Viacheslav Ovsiienko Date: Mon, 8 Nov 2021 18:41:01 +0200 Subject: [PATCH] doc: describe timestamp limitations for mlx5 Cc: Xueming Li [ upstream commit 1a3709c1f021afbe58db4a27a179127e561fe401 ] The ConnectX NIC series hardware provides only 63-bit wide timestamps. The imposed limitations description added to documentation. At the moment there are no affected applications known or bug reports neither, this is just the declaration of limitation. Signed-off-by: Viacheslav Ovsiienko --- doc/guides/nics/mlx5.rst | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 84e58fc27b..ac3e148b2d 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -338,6 +338,20 @@ Limitations - Hairpin between two ports could only manual binding and explicit Tx flow mode. For single port hairpin, all the combinations of auto/manual binding and explicit/implicit Tx flow mode could be supported. - Hairpin in switchdev SR-IOV mode is not supported till now. +- Timestamps: + + - CQE timestamp field width is limited by hardware to 63 bits, MSB is zero. + - In the free-running mode the timestamp counter is reset on power on + and 63-bit value provides over 1800 years of uptime till overflow. + - In the real-time mode + (configurable with ``REAL_TIME_CLOCK_ENABLE`` firmware settings), + the timestamp presents the nanoseconds elapsed since 01-Jan-1970, + hardware timestamp overflow will happen on 19-Jan-2038 + (0x80000000 seconds since 01-Jan-1970). + - The send scheduling is based on timestamps + from the reference "Clock Queue" completions, + the scheduled send timestamps should not be specified with non-zero MSB. + Statistics ---------- @@ -1035,6 +1049,10 @@ Below are some firmware configurations listed. FLEX_PARSER_PROFILE_ENABLE=4 PROG_PARSE_GRAPH=1 +- enable realtime timestamp format:: + + REAL_TIME_CLOCK_ENABLE=1 + Prerequisites ------------- -- 2.34.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-11-28 22:41:04.119783495 +0800 +++ 0011-doc-describe-timestamp-limitations-for-mlx5.patch 2021-11-28 22:41:03.216876184 +0800 @@ -1 +1 @@ -From 1a3709c1f021afbe58db4a27a179127e561fe401 Mon Sep 17 00:00:00 2001 +From fdb91c91e807780d48e50e3f6158f0173f48c28c Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 1a3709c1f021afbe58db4a27a179127e561fe401 ] @@ -14,2 +16,0 @@ -Cc: stable@dpdk.org - @@ -22 +23 @@ -index d175c2061e..552e06c0db 100644 +index 84e58fc27b..ac3e148b2d 100644 @@ -25,3 +26,3 @@ -@@ -480,6 +480,20 @@ Limitations - - - Needs OFED 5.4+. +@@ -338,6 +338,20 @@ Limitations + - Hairpin between two ports could only manual binding and explicit Tx flow mode. For single port hairpin, all the combinations of auto/manual binding and explicit/implicit Tx flow mode could be supported. + - Hairpin in switchdev SR-IOV mode is not supported till now. @@ -46 +47 @@ -@@ -1242,6 +1256,10 @@ Below are some firmware configurations listed. +@@ -1035,6 +1049,10 @@ Below are some firmware configurations listed. @@ -54,2 +55,2 @@ - Linux Prerequisites - ------------------- + Prerequisites + -------------