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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT040.mail.protection.outlook.com (10.13.177.166) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4734.22 via Frontend Transport; Sun, 28 Nov 2021 15:00:02 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 28 Nov 2021 15:00:00 +0000 From: Xueming Li To: Gregory Etelson CC: Luca Boccassi , Viacheslav Ovsiienko , dpdk stable Subject: patch 'net/mlx5: fix GENEVE protocol type translation' has been queued to stable release 20.11.4 Date: Sun, 28 Nov 2021 22:53:51 +0800 Message-ID: <20211128145423.3974892-48-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211128145423.3974892-1-xuemingl@nvidia.com> References: <20211110063216.2744012-1-xuemingl@nvidia.com> <20211128145423.3974892-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 35345ae4-c1b4-42fd-84b3-08d9b27fc185 X-MS-TrafficTypeDiagnostic: CY4PR1201MB0181: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(2906002)(82310400004)(54906003)(7696005)(26005)(37006003)(5660300002)(40140700001)(966005)(47076005)(55016003)(8936002)(356005)(508600001)(36860700001)(83380400001)(4001150100001)(7636003)(316002)(2616005)(8676002)(6862004)(6636002)(70206006)(70586007)(4326008)(426003)(16526019)(86362001)(336012)(186003)(6286002)(1076003)(6666004)(53546011)(36756003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2021 15:00:02.5290 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 35345ae4-c1b4-42fd-84b3-08d9b27fc185 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1201MB0181 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 20.11.4 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/30/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/fdae4c228feb436202527ea8c2e919139c4f95e1 Thanks. Xueming Li --- >From fdae4c228feb436202527ea8c2e919139c4f95e1 Mon Sep 17 00:00:00 2001 From: Gregory Etelson Date: Sun, 14 Nov 2021 17:36:15 +0200 Subject: [PATCH] net/mlx5: fix GENEVE protocol type translation Cc: Xueming Li [ upstream commit 690391dd0e8bc7a8d02a3aba844ffc3dffe7aecd ] When application creates several flows to match on GENEVE tunnel without explicitly specifying GENEVE protocol type value in flow rules, PMD will translate that to zero mask. RDMA-CORE cannot distinguish between different inner flow types and produces identical matchers for each zero mask. The patch extracts inner header type from flow rule and forces it in GENEVE protocol type, if application did not specify any without explicitly specifying GENEVE protocol type value in flow rules, protocol type value. Fixes: e59a5dbcfd07 ("net/mlx5: add flow match on GENEVE item") Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_dv.c | 78 ++++++++++++++++++++------------- 1 file changed, 47 insertions(+), 31 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 27a6554c7e..b80bdc78ba 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -84,6 +84,20 @@ flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev, static void flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss); +static inline uint16_t +mlx5_translate_tunnel_etypes(uint64_t pattern_flags) +{ + if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2) + return RTE_ETHER_TYPE_TEB; + else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) + return RTE_ETHER_TYPE_IPV4; + else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6) + return RTE_ETHER_TYPE_IPV6; + else if (pattern_flags & MLX5_FLOW_LAYER_MPLS) + return RTE_ETHER_TYPE_MPLS; + return 0; +} + /** * Initialize flow attributes structure according to flow items' types. * @@ -7258,49 +7272,39 @@ flow_dv_translate_item_vxlan_gpe(void *matcher, void *key, static void flow_dv_translate_item_geneve(void *matcher, void *key, - const struct rte_flow_item *item, int inner) + const struct rte_flow_item *item, + uint64_t pattern_flags) { + static const struct rte_flow_item_geneve empty_geneve = {0,}; const struct rte_flow_item_geneve *geneve_m = item->mask; const struct rte_flow_item_geneve *geneve_v = item->spec; - void *headers_m; - void *headers_v; + /* GENEVE flow item validation allows single tunnel item */ + void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers); + void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers); void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters); void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters); - uint16_t dport; uint16_t gbhdr_m; uint16_t gbhdr_v; - char *vni_m; - char *vni_v; - size_t size, i; + char *vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni); + char *vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni); + size_t size = sizeof(geneve_m->vni), i; + uint16_t protocol_m, protocol_v; - if (inner) { - headers_m = MLX5_ADDR_OF(fte_match_param, matcher, - inner_headers); - headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers); - } else { - headers_m = MLX5_ADDR_OF(fte_match_param, matcher, - outer_headers); - headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers); - } - dport = MLX5_UDP_PORT_GENEVE; if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) { MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF); - MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport); + MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, + MLX5_UDP_PORT_GENEVE); + } + if (!geneve_v) { + geneve_v = &empty_geneve; + geneve_m = &empty_geneve; + } else { + if (!geneve_m) + geneve_m = &rte_flow_item_geneve_mask; } - if (!geneve_v) - return; - if (!geneve_m) - geneve_m = &rte_flow_item_geneve_mask; - size = sizeof(geneve_m->vni); - vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni); - vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni); memcpy(vni_m, geneve_m->vni, size); for (i = 0; i < size; ++i) vni_v[i] = vni_m[i] & geneve_v->vni[i]; - MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type, - rte_be_to_cpu_16(geneve_m->protocol)); - MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type, - rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol)); gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0); gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0); MLX5_SET(fte_match_set_misc, misc_m, geneve_oam, @@ -7312,6 +7316,16 @@ flow_dv_translate_item_geneve(void *matcher, void *key, MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len, MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) & MLX5_GENEVE_OPTLEN_VAL(gbhdr_m)); + protocol_m = rte_be_to_cpu_16(geneve_m->protocol); + protocol_v = rte_be_to_cpu_16(geneve_v->protocol); + if (!protocol_m) { + /* Force next protocol to prevent matchers duplication */ + protocol_m = 0xFFFF; + protocol_v = mlx5_translate_tunnel_etypes(pattern_flags); + } + MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type, protocol_m); + MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type, + protocol_m & protocol_v); } /** @@ -10561,10 +10575,9 @@ flow_dv_translate(struct rte_eth_dev *dev, tunnel_item = items; break; case RTE_FLOW_ITEM_TYPE_GENEVE: - flow_dv_translate_item_geneve(match_mask, match_value, - items, tunnel); matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); last_item = MLX5_FLOW_LAYER_GENEVE; + tunnel_item = items; break; case RTE_FLOW_ITEM_TYPE_MPLS: flow_dv_translate_item_mpls(match_mask, match_value, @@ -10656,6 +10669,9 @@ flow_dv_translate(struct rte_eth_dev *dev, if (item_flags & MLX5_FLOW_LAYER_VXLAN_GPE) flow_dv_translate_item_vxlan_gpe(match_mask, match_value, tunnel_item, item_flags); + else if (item_flags & MLX5_FLOW_LAYER_GENEVE) + flow_dv_translate_item_geneve(match_mask, match_value, + tunnel_item, item_flags); #ifdef RTE_LIBRTE_MLX5_DEBUG MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf, dev_flow->dv.value.buf)); -- 2.34.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-11-28 22:41:05.755107120 +0800 +++ 0047-net-mlx5-fix-GENEVE-protocol-type-translation.patch 2021-11-28 22:41:03.356873650 +0800 @@ -1 +1 @@ -From 690391dd0e8bc7a8d02a3aba844ffc3dffe7aecd Mon Sep 17 00:00:00 2001 +From fdae4c228feb436202527ea8c2e919139c4f95e1 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 690391dd0e8bc7a8d02a3aba844ffc3dffe7aecd ] @@ -18 +20,0 @@ -Cc: stable@dpdk.org @@ -27 +29 @@ -index f9acb69cca..bce504391d 100644 +index 27a6554c7e..b80bdc78ba 100644 @@ -30,3 +32,3 @@ -@@ -93,6 +93,20 @@ static int - flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev, - uint32_t rix_jump); +@@ -84,6 +84,20 @@ flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev, + static void + flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss); @@ -48,4 +50,4 @@ - static int16_t - flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev) - { -@@ -9038,49 +9052,39 @@ flow_dv_translate_item_vxlan_gpe(void *matcher, void *key, + /** + * Initialize flow attributes structure according to flow items' types. + * +@@ -7258,49 +7272,39 @@ flow_dv_translate_item_vxlan_gpe(void *matcher, void *key, @@ -120 +122 @@ -@@ -9092,6 +9096,16 @@ flow_dv_translate_item_geneve(void *matcher, void *key, +@@ -7312,6 +7316,16 @@ flow_dv_translate_item_geneve(void *matcher, void *key, @@ -137 +139 @@ -@@ -13449,10 +13463,9 @@ flow_dv_translate(struct rte_eth_dev *dev, +@@ -10561,10 +10575,9 @@ flow_dv_translate(struct rte_eth_dev *dev, @@ -147,3 +149,3 @@ - case RTE_FLOW_ITEM_TYPE_GENEVE_OPT: - ret = flow_dv_translate_item_geneve_opt(dev, match_mask, -@@ -13581,6 +13594,9 @@ flow_dv_translate(struct rte_eth_dev *dev, + case RTE_FLOW_ITEM_TYPE_MPLS: + flow_dv_translate_item_mpls(match_mask, match_value, +@@ -10656,6 +10669,9 @@ flow_dv_translate(struct rte_eth_dev *dev,