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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT026.mail.protection.outlook.com (10.13.172.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4734.22 via Frontend Transport; Sun, 28 Nov 2021 14:55:18 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 28 Nov 2021 14:55:16 +0000 From: Xueming Li To: Michael Baum CC: Luca Boccassi , Matan Azrad , "dpdk stable" Subject: patch 'net/mlx5: workaround MR creation for flow counter' has been queued to stable release 20.11.4 Date: Sun, 28 Nov 2021 22:53:09 +0800 Message-ID: <20211128145423.3974892-6-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211128145423.3974892-1-xuemingl@nvidia.com> References: <20211110063216.2744012-1-xuemingl@nvidia.com> <20211128145423.3974892-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7e7f8e94-c9d2-4e31-8f0a-08d9b27f17f9 X-MS-TrafficTypeDiagnostic: MN2PR12MB4392: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(426003)(4326008)(40140700001)(8676002)(30864003)(336012)(53546011)(6666004)(8936002)(6286002)(70586007)(83380400001)(26005)(186003)(7636003)(36860700001)(6636002)(356005)(1076003)(16526019)(7696005)(36756003)(5660300002)(70206006)(6862004)(47076005)(4001150100001)(55016003)(37006003)(82310400004)(2906002)(966005)(54906003)(86362001)(508600001)(316002)(2616005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2021 14:55:18.0948 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e7f8e94-c9d2-4e31-8f0a-08d9b27f17f9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4392 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 20.11.4 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/30/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/3088dda469407fe71c930a41a78f06582b509bdd Thanks. Xueming Li --- >From 3088dda469407fe71c930a41a78f06582b509bdd Mon Sep 17 00:00:00 2001 From: Michael Baum Date: Tue, 9 Nov 2021 14:36:12 +0200 Subject: [PATCH] net/mlx5: workaround MR creation for flow counter Cc: Xueming Li [ upstream commit 8451e165b8b2f0503922b03c27a754d646a4e5b4 ] Due to kernel driver / FW issues in direct MKEY creation using the DevX API, this patch replaces the counter MR creation to use wrapped mkey API. Fixes: 5382d28c2110 ("net/mlx5: accelerate DV flow counter transactions") Signed-off-by: Michael Baum Signed-off-by: Matan Azrad --- drivers/net/mlx5/linux/mlx5_os.c | 10 ---------- drivers/net/mlx5/mlx5.c | 3 +-- drivers/net/mlx5/mlx5.h | 5 +---- drivers/net/mlx5/mlx5_flow.c | 28 ++++++---------------------- 4 files changed, 8 insertions(+), 38 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index e4bb26bc2b..3128fb3e5e 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1184,16 +1184,6 @@ err_secondary: err = -err; goto error; } - /* Check relax ordering support. */ - if (!haswell_broadwell_cpu) { - sh->cmng.relaxed_ordering_write = - config->hca_attr.relaxed_ordering_write; - sh->cmng.relaxed_ordering_read = - config->hca_attr.relaxed_ordering_read; - } else { - sh->cmng.relaxed_ordering_read = 0; - sh->cmng.relaxed_ordering_write = 0; - } sh->rq_ts_format = config->hca_attr.rq_ts_format; sh->sq_ts_format = config->hca_attr.sq_ts_format; sh->qp_ts_format = config->hca_attr.qp_ts_format; diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index d094e9e423..800ca6af0a 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -477,8 +477,7 @@ mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data; LIST_REMOVE(mng, next); - claim_zero(mlx5_devx_cmd_destroy(mng->dm)); - claim_zero(mlx5_glue->devx_umem_dereg(mng->umem)); + mlx5_os_wrapped_mkey_destroy(&mng->wm); mlx5_free(mem); } diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 4b0a97f246..2a040453a6 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -423,8 +423,7 @@ struct mlx5_flow_counter_pool { struct mlx5_counter_stats_mem_mng { LIST_ENTRY(mlx5_counter_stats_mem_mng) next; struct mlx5_counter_stats_raw *raws; - struct mlx5_devx_obj *dm; - void *umem; + struct mlx5_pmd_wrapped_mr wm; }; /* Raw memory structure for the counter statistics values of a pool. */ @@ -455,8 +454,6 @@ struct mlx5_flow_counter_mng { uint8_t pending_queries; uint16_t pool_index; uint8_t query_thread_on; - bool relaxed_ordering_read; - bool relaxed_ordering_write; bool counter_fallback; /* Use counter fallback management. */ LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 5f44af5fa6..49619d95e1 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -6496,7 +6496,6 @@ mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, static int mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) { - struct mlx5_devx_mkey_attr mkey_attr; struct mlx5_counter_stats_mem_mng *mem_mng; volatile struct flow_counter_stats *raw_data; int raws_n = MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES; @@ -6506,6 +6505,7 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) sizeof(struct mlx5_counter_stats_mem_mng); size_t pgsize = rte_mem_page_size(); uint8_t *mem; + int ret; int i; if (pgsize == (size_t)-1) { @@ -6520,26 +6520,10 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) } mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1; size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n; - mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size, - IBV_ACCESS_LOCAL_WRITE); - if (!mem_mng->umem) { - rte_errno = errno; - mlx5_free(mem); - return -rte_errno; - } - mkey_attr.addr = (uintptr_t)mem; - mkey_attr.size = size; - mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem); - mkey_attr.pd = sh->pdn; - mkey_attr.log_entity_size = 0; - mkey_attr.pg_access = 0; - mkey_attr.klm_array = NULL; - mkey_attr.klm_num = 0; - mkey_attr.relaxed_ordering_write = sh->cmng.relaxed_ordering_write; - mkey_attr.relaxed_ordering_read = sh->cmng.relaxed_ordering_read; - mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr); - if (!mem_mng->dm) { - mlx5_glue->devx_umem_dereg(mem_mng->umem); + ret = mlx5_os_wrapped_mkey_create(sh->ctx, sh->pd, + sh->pdn, mem, size, + &mem_mng->wm); + if (ret) { rte_errno = errno; mlx5_free(mem); return -rte_errno; @@ -6658,7 +6642,7 @@ mlx5_flow_query_alarm(void *arg) ret = mlx5_devx_cmd_flow_counter_query(pool->min_dcs, 0, MLX5_COUNTERS_PER_POOL, NULL, NULL, - pool->raw_hw->mem_mng->dm->id, + pool->raw_hw->mem_mng->wm.lkey, (void *)(uintptr_t) pool->raw_hw->data, sh->devx_comp, -- 2.34.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-11-28 22:41:03.810717714 +0800 +++ 0005-net-mlx5-workaround-MR-creation-for-flow-counter.patch 2021-11-28 22:41:03.193543273 +0800 @@ -1 +1 @@ -From 8451e165b8b2f0503922b03c27a754d646a4e5b4 Mon Sep 17 00:00:00 2001 +From 3088dda469407fe71c930a41a78f06582b509bdd Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 8451e165b8b2f0503922b03c27a754d646a4e5b4 ] @@ -11 +13,0 @@ -Cc: stable@dpdk.org @@ -16,4 +18,5 @@ - drivers/net/mlx5/mlx5.c | 8 +------- - drivers/net/mlx5/mlx5.h | 5 +---- - drivers/net/mlx5/mlx5_flow.c | 25 ++++++------------------- - 3 files changed, 8 insertions(+), 30 deletions(-) + drivers/net/mlx5/linux/mlx5_os.c | 10 ---------- + drivers/net/mlx5/mlx5.c | 3 +-- + drivers/net/mlx5/mlx5.h | 5 +---- + drivers/net/mlx5/mlx5_flow.c | 28 ++++++---------------------- + 4 files changed, 8 insertions(+), 38 deletions(-) @@ -20,0 +24,21 @@ +diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c +index e4bb26bc2b..3128fb3e5e 100644 +--- a/drivers/net/mlx5/linux/mlx5_os.c ++++ b/drivers/net/mlx5/linux/mlx5_os.c +@@ -1184,16 +1184,6 @@ err_secondary: + err = -err; + goto error; + } +- /* Check relax ordering support. */ +- if (!haswell_broadwell_cpu) { +- sh->cmng.relaxed_ordering_write = +- config->hca_attr.relaxed_ordering_write; +- sh->cmng.relaxed_ordering_read = +- config->hca_attr.relaxed_ordering_read; +- } else { +- sh->cmng.relaxed_ordering_read = 0; +- sh->cmng.relaxed_ordering_write = 0; +- } + sh->rq_ts_format = config->hca_attr.rq_ts_format; + sh->sq_ts_format = config->hca_attr.sq_ts_format; + sh->qp_ts_format = config->hca_attr.qp_ts_format; @@ -22 +46 @@ -index f5990dd757..2a3efb3588 100644 +index d094e9e423..800ca6af0a 100644 @@ -25,20 +49 @@ -@@ -522,7 +522,6 @@ mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh) - static void - mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh) - { -- struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr; - int i; - - memset(&sh->cmng, 0, sizeof(sh->cmng)); -@@ -535,10 +534,6 @@ mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh) - TAILQ_INIT(&sh->cmng.counters[i]); - rte_spinlock_init(&sh->cmng.csl[i]); - } -- if (sh->devx && !haswell_broadwell_cpu) { -- sh->cmng.relaxed_ordering_write = attr->relaxed_ordering_write; -- sh->cmng.relaxed_ordering_read = attr->relaxed_ordering_read; -- } - } - - /** -@@ -553,8 +548,7 @@ mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) +@@ -477,8 +477,7 @@ mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) @@ -49 +54 @@ -- claim_zero(mlx5_os_umem_dereg(mng->umem)); +- claim_zero(mlx5_glue->devx_umem_dereg(mng->umem)); @@ -55 +60 @@ -index c2a13b6de4..bdadd6e024 100644 +index 4b0a97f246..2a040453a6 100644 @@ -58 +63 @@ -@@ -462,8 +462,7 @@ struct mlx5_flow_counter_pool { +@@ -423,8 +423,7 @@ struct mlx5_flow_counter_pool { @@ -68 +73 @@ -@@ -494,8 +493,6 @@ struct mlx5_flow_counter_mng { +@@ -455,8 +454,6 @@ struct mlx5_flow_counter_mng { @@ -78 +83 @@ -index 2f30a35525..40625688b0 100644 +index 5f44af5fa6..49619d95e1 100644 @@ -81 +86 @@ -@@ -7775,7 +7775,6 @@ mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, +@@ -6496,7 +6496,6 @@ mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, @@ -89 +94 @@ -@@ -7785,6 +7784,7 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) +@@ -6506,6 +6505,7 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) @@ -97 +102 @@ -@@ -7799,23 +7799,10 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) +@@ -6520,26 +6520,10 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) @@ -101 +106 @@ -- mem_mng->umem = mlx5_os_umem_reg(sh->cdev->ctx, mem, size, +- mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size, @@ -108 +112,0 @@ -- memset(&mkey_attr, 0, sizeof(mkey_attr)); @@ -112 +116,5 @@ -- mkey_attr.pd = sh->cdev->pdn; +- mkey_attr.pd = sh->pdn; +- mkey_attr.log_entity_size = 0; +- mkey_attr.pg_access = 0; +- mkey_attr.klm_array = NULL; +- mkey_attr.klm_num = 0; @@ -115 +123 @@ -- mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->cdev->ctx, &mkey_attr); +- mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr); @@ -117,3 +125,3 @@ -- mlx5_os_umem_dereg(mem_mng->umem); -+ ret = mlx5_os_wrapped_mkey_create(sh->cdev->ctx, sh->cdev->pd, -+ sh->cdev->pdn, mem, size, +- mlx5_glue->devx_umem_dereg(mem_mng->umem); ++ ret = mlx5_os_wrapped_mkey_create(sh->ctx, sh->pd, ++ sh->pdn, mem, size, @@ -125 +133 @@ -@@ -7934,7 +7921,7 @@ mlx5_flow_query_alarm(void *arg) +@@ -6658,7 +6642,7 @@ mlx5_flow_query_alarm(void *arg)