From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5629BA0C4C for ; Wed, 1 Dec 2021 08:48:27 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 70C75411FB; Wed, 1 Dec 2021 08:48:26 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 0379F411EB for ; Wed, 1 Dec 2021 08:48:24 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 75178106F; Tue, 30 Nov 2021 23:48:24 -0800 (PST) Received: from net-arm-n1amp-02.shanghai.arm.com (net-arm-n1amp-02.shanghai.arm.com [10.169.210.110]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9F9103F766; Tue, 30 Nov 2021 23:48:22 -0800 (PST) From: Ruifeng Wang To: stable@dpdk.org Cc: christian.ehrhardt@canonical.com, nd@arm.com, Ruifeng Wang , Honnappa Nagarahalli Subject: [PATCH 19.11] net/i40e: fix risk in descriptor read in NEON Rx Date: Wed, 1 Dec 2021 15:48:11 +0800 Message-Id: <20211201074811.1590896-1-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org [ upstream commit 778602fe570a138224de94a38eca3ce2e344138c ] Rx descriptor is 16B/32B in size. If the DD bit is set, it indicates that the rest of the descriptor words have valid values. Hence, the word containing DD bit must be read first before reading the rest of the descriptor words. In NEON vector PMD, vector load loads two contiguous 8B of descriptor data into vector register. Given vector load ensures no 16B atomicity, read of the word that includes DD field could be reordered after read of other words. In this case, some words could contain invalid data. Read barrier is added after read of qword1 that includes DD field. And qword0 is reloaded to update vector register. This ensures that the fetched data is correct. Testpmd single core test on N1SDP/ThunderX2 showed no performance drop. Fixes: ae0eb310f253 ("net/i40e: implement vector PMD for ARM") Signed-off-by: Ruifeng Wang Reviewed-by: Honnappa Nagarahalli --- drivers/net/i40e/i40e_rxtx_vec_neon.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/i40e/i40e_rxtx_vec_neon.c b/drivers/net/i40e/i40e_rxtx_vec_neon.c index bd1e0490d..0da6b37da 100644 --- a/drivers/net/i40e/i40e_rxtx_vec_neon.c +++ b/drivers/net/i40e/i40e_rxtx_vec_neon.c @@ -299,6 +299,14 @@ _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts, /* B.2 copy 2 mbuf point into rx_pkts */ vst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2); + /* Use acquire fence to order loads of descriptor qwords */ + __atomic_thread_fence(__ATOMIC_ACQUIRE); + /* A.2 reload qword0 to make it ordered after qword1 load */ + descs[3] = vld1q_lane_u64((uint64_t *)(rxdp + 3), descs[3], 0); + descs[2] = vld1q_lane_u64((uint64_t *)(rxdp + 2), descs[2], 0); + descs[1] = vld1q_lane_u64((uint64_t *)(rxdp + 1), descs[1], 0); + descs[0] = vld1q_lane_u64((uint64_t *)(rxdp), descs[0], 0); + if (split_packet) { rte_mbuf_prefetch_part2(rx_pkts[pos]); rte_mbuf_prefetch_part2(rx_pkts[pos + 1]); -- 2.25.1