From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DB9EAA0548 for ; Thu, 2 Dec 2021 17:01:33 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D2ED24067B; Thu, 2 Dec 2021 17:01:33 +0100 (CET) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2077.outbound.protection.outlook.com [40.107.223.77]) by mails.dpdk.org (Postfix) with ESMTP id F2F304067B for ; Thu, 2 Dec 2021 17:01:32 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QirJtx2kcJMZRbIaZyaOTrzQ9GTmqNQcuw3TFT4tuv1F8OlGQwKqJ+QZHvO8PUATPsMOuv+cuaFRDUK6oCwqLPZurkNsGphnJE86Gu/XVe5X+Wpf2KhkqhRQtnX69QngPCDuTYt+aATeipBmpvhl/4sZod0KwI4wqx+KB6RkDf+UxYc+4Uats9OlhebxUDWAoR/kEXjkVFpZ2c3DH2OddLJ5l8G24mZGp+bLibOYE0Kr2GXIBQXFPX98cltMN2bcpWkxuyRCQ+qF5mpdC7zhca1YQBl1RfMYC6y9Iq06/G8DkYC9oyhA72m+vCRYbfV1oSdMm3U+7lQKGjRAiRi2Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ZMnJSljvlJUF+2Td2chy/P7C3fFDXpKUmIbtZ9faWLY=; b=S+f68s6dTqW4wWuKKbP1RPw1FWomZSZrwk4KcfmalxGbPhWUfZLuW85vAo4WBXH+XUUGFNb7GJhfgG0bS8jfSeXu7Ue/4DqdFqVELYmzhwD+cEUwiPk7aNMGUFcVoc7nHG+HnN6DY8YE42GcX5Nxy5f6vauA0nJxaCmC47ZV2Vk6t6FEBIq8aZ4LTnS5hu8xyHV7finuA3I4ffQS98LjaSFRmJIa/DvjAZ26QkPB4XrrkZNvKEaEsgEq0Va9mhkm4MuYq+5b/pD/cnNHLBmkMt6Khp0yyTdIkNeVAqawjOoPcuift0wScSOj+pk72u7/ZHDSpJVKxk3FlXV1nq9yPg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.32) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZMnJSljvlJUF+2Td2chy/P7C3fFDXpKUmIbtZ9faWLY=; b=MA/DAyQwGNo6Vl4gs44MnXHpJdcav2NU9l1B9idHe5xYPMSkEyS2e9huuuwbUXoKJDaNCwxDFcd2bCXIRq28/ALOO9APbY0RhvncrP6j4oDnT2qZUFJT7Z9c9j3TOsUtXbCummsDQmxRgs7BATc+IhJASx+qwXnN8yifIsHDwj4f2wXlvorwnzgyOAwcvnK3AmCwV36bjO3W/b8aKDvUQegiZqS6EKzo2c56av08qoF2yBZmpbaxlwdwUwhyEfarspIXOrS6+HmkD2ts/QEF2+tnkHlcjdBKpuAm6FUV8NcH2luorGMkUBP/1XSW9IqbR7Iq1TYnGMtHQSXKmrHlCg== Received: from BN0PR03CA0008.namprd03.prod.outlook.com (2603:10b6:408:e6::13) by BY5PR12MB3746.namprd12.prod.outlook.com (2603:10b6:a03:1a7::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4755.11; Thu, 2 Dec 2021 16:01:30 +0000 Received: from BN8NAM11FT034.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e6:cafe::e7) by BN0PR03CA0008.outlook.office365.com (2603:10b6:408:e6::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4755.14 via Frontend Transport; Thu, 2 Dec 2021 16:01:30 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.32) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.32 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.32; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.32) by BN8NAM11FT034.mail.protection.outlook.com (10.13.176.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4755.13 via Frontend Transport; Thu, 2 Dec 2021 16:01:30 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 2 Dec 2021 08:00:46 -0800 Received: from nvidia.com (172.20.187.6) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.986.9; Thu, 2 Dec 2021 08:00:44 -0800 From: Gregory Etelson To: , CC: Viacheslav Ovsiienko , Matan Azrad , Shahaf Shuler , Raslan Darawsheh Subject: [PATCH 19.11 1/6] net/mlx5: fix VXLAN-GPE next protocol translation Date: Thu, 2 Dec 2021 18:00:14 +0200 Message-ID: <20211202160019.26453-1-getelson@nvidia.com> X-Mailer: git-send-email 2.34.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b466d7cd-d2b8-42a5-cd4c-08d9b5ad0122 X-MS-TrafficTypeDiagnostic: BY5PR12MB3746: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:389; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wWzYTGBau3LwjE7HCZpoqOpWGq0SW2hiHKMxN/gEu0Djp5gKMPDy5ZbT5EkGU4iiT3FGXB0ncQQkWSx8uShIh/MU3ed1taU9iss3iL44HktfO7d071nRoHVYC/XH/dPaqMLn8IsCnU9G6cfaSbh+MJVdxDN/WoiAHHg18UGvI7LqI6nrlbEFQXC9yqFHvpasShkAxL11K1+yq144ulINVO655bUB5byOCqiH04Ew8T+bZeZOBfBWBsjJeYsATfgETOczm2/m7gOFPQVzHIroTG0DozemIIM2ME9nZIT+TwxK2kSk+fZJqVYyirs5FLJwo9Asg62t7ulFHJXqOGqDTaxphFLjQ8l/yl+xddwXEWNUZMmr9BnBoqaCsKcsUAi8DVbj1Apnn4EF2WZ7d9YnLGHSD78MKwYNzTLfyUcvnv/ZTXwh3dz7itKhXJd/8qYWt1nIXdQmgiCr7mbUI0B9jegmNbmGa2FgG7UvPLNW5fr5O6oEeBOSwLRswVHexarKCWpJpD7AMV5556j9gafkp3tqFdeBeWD8AQ42az1+8n1lek/Zi9aRg0R8WB2lsj5sZjwGxxVINYpYh4DQovVLkGiI+CcHO9VPDfeJYfUd6DwqTnpim+J/gc47ldv/ORH37HUoRmfnaVNGET2MjsRQSbKkhT8KTtuHBOgj2Q48xFSA+jQw1PD/LOg+ppPeRX9BCrNUCcpZ55OyHY0tX3e6USPyJJElOiRrOyhWSN2GFsr9MQVkJxMdt3JayUa4Wfg4jmzD17tKTBmrUX1GumylWQ== X-Forefront-Antispam-Report: CIP:216.228.112.32; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid01.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(40470700001)(5660300002)(336012)(107886003)(83380400001)(426003)(2616005)(47076005)(86362001)(8936002)(55016003)(7636003)(26005)(40460700001)(82310400004)(508600001)(36756003)(4326008)(8676002)(70206006)(316002)(7696005)(356005)(2906002)(186003)(7049001)(16526019)(36860700001)(6286002)(6666004)(54906003)(70586007)(1076003)(110136005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2021 16:01:30.0788 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b466d7cd-d2b8-42a5-cd4c-08d9b5ad0122 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.32]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3746 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org [ upstream commit 861fa3796f75748ccc4a6dae55e5a7e34c97dea4 ] VXLAN-GPE extends VXLAN protocol and provides the next protocol field specifying the first inner header type. The application can assign some explicit value to VXLAN-GPE::next_protocol field or set it to the default one. In the latter case, the rdma-core library cannot recognize the matcher built by PMD correctly, and it results in hardware configuration missing inner headers match. The patch forces VXLAN-GPE::next_protocol assignment if the application did not explicitly assign it to the non-default value Fixes: 90456726eb80 ("net/mlx5: fix VXLAN-GPE item translation") Cc: stable@dpdk.org Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_dv.c | 76 ++++++++++++++++++--------------- 1 file changed, 42 insertions(+), 34 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index f8ca36b1c6..f124f42c9c 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -6056,46 +6056,40 @@ flow_dv_translate_item_vxlan(void *matcher, void *key, static void flow_dv_translate_item_vxlan_gpe(void *matcher, void *key, - const struct rte_flow_item *item, int inner) + const struct rte_flow_item *item, + const uint64_t pattern_flags) { + static const struct rte_flow_item_vxlan_gpe dummy_vxlan_gpe_hdr = {0, }; const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask; const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec; - void *headers_m; - void *headers_v; + /* The item was validated to be on the outer side */ + void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers); + void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers); void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3); void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3); - char *vni_m; - char *vni_v; - uint16_t dport; - int size; - int i; + char *vni_m = + MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni); + char *vni_v = + MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni); + int i, size = sizeof(vxlan_m->vni); uint8_t flags_m = 0xff; uint8_t flags_v = 0xc; + uint8_t m_protocol, v_protocol; - if (inner) { - headers_m = MLX5_ADDR_OF(fte_match_param, matcher, - inner_headers); - headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers); - } else { - headers_m = MLX5_ADDR_OF(fte_match_param, matcher, - outer_headers); - headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers); - } - dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ? - MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE; if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) { MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF); - MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport); + MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, + MLX5_UDP_PORT_VXLAN_GPE); + } + if (!vxlan_v) { + vxlan_v = &dummy_vxlan_gpe_hdr; + vxlan_m = &dummy_vxlan_gpe_hdr; + } else { + if (!vxlan_m) + vxlan_m = &rte_flow_item_vxlan_gpe_mask; } - if (!vxlan_v) - return; - if (!vxlan_m) - vxlan_m = &rte_flow_item_vxlan_gpe_mask; - size = sizeof(vxlan_m->vni); - vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni); - vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni); memcpy(vni_m, vxlan_m->vni, size); for (i = 0; i < size; ++i) vni_v[i] = vni_m[i] & vxlan_v->vni[i]; @@ -6105,10 +6099,22 @@ flow_dv_translate_item_vxlan_gpe(void *matcher, void *key, } MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m); MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v); - MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol, - vxlan_m->protocol); - MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol, - vxlan_v->protocol); + m_protocol = vxlan_m->protocol; + v_protocol = vxlan_v->protocol; + if (!m_protocol) { + m_protocol = 0xff; + /* Force next protocol to ensure next headers parsing. */ + if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2) + v_protocol = RTE_VXLAN_GPE_TYPE_ETH; + else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) + v_protocol = RTE_VXLAN_GPE_TYPE_IPV4; + else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6) + v_protocol = RTE_VXLAN_GPE_TYPE_IPV6; + } + MLX5_SET(fte_match_set_misc3, misc_m, + outer_vxlan_gpe_next_protocol, m_protocol); + MLX5_SET(fte_match_set_misc3, misc_v, + outer_vxlan_gpe_next_protocol, m_protocol & v_protocol); } /** @@ -7237,6 +7243,7 @@ __flow_dv_translate(struct rte_eth_dev *dev, struct rte_vlan_hdr vlan = { 0 }; uint32_t table; int ret = 0; + const struct rte_flow_item *tunnel_item = NULL; mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX : MLX5DV_FLOW_TABLE_TYPE_NIC_RX; @@ -7793,12 +7800,10 @@ __flow_dv_translate(struct rte_eth_dev *dev, last_item = MLX5_FLOW_LAYER_VXLAN; break; case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: - flow_dv_translate_item_vxlan_gpe(match_mask, - match_value, items, - tunnel); matcher.priority = flow->rss.level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4; last_item = MLX5_FLOW_LAYER_VXLAN_GPE; + tunnel_item = items; break; case RTE_FLOW_ITEM_TYPE_GENEVE: flow_dv_translate_item_geneve(match_mask, match_value, @@ -7868,6 +7873,9 @@ __flow_dv_translate(struct rte_eth_dev *dev, match_value, NULL)) return -rte_errno; } + if (item_flags & MLX5_FLOW_LAYER_VXLAN_GPE) + flow_dv_translate_item_vxlan_gpe(match_mask, match_value, + tunnel_item, item_flags); assert(!flow_dv_check_valid_spec(matcher.mask.buf, dev_flow->dv.value.buf)); /* -- 2.34.0