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[89.79.181.52]) by smtp.gmail.com with ESMTPSA id h2sm2777232wrz.23.2021.12.03.07.09.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Dec 2021 07:09:18 -0800 (PST) From: Michal Krawczyk To: stable@dpdk.org Cc: christian.ehrhardt@canonical.com, Michal Krawczyk , Igor Chauskin , Shai Brandes Subject: [PATCH 19.11 1/4] net/ena: fix offload capabilities verification Date: Fri, 3 Dec 2021 16:08:56 +0100 Message-Id: <20211203150859.3933-1-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org [ upstream commit e8c838fde93f48c2a7504570aae38c06e3189fa1 ] ENA PMD has multiple checksum offload flags, which are more discrete than the DPDK offload capabilities flags. As the driver wasn't storing it's internal checksum offload capabilities and was relying only on the DPDK capabilities, not all scenarios could be properly covered (like when to prepare pseudo header checksum and when not). Moreover, the user could request offload capability, which isn't supported by the HW and the PMD would quietly ignore the issue. This commit reworks eth_ena_prep_pkts() function to perform additional checks and to properly reflect the HW requirements. With the RTE_LIBRTE_ETHDEV_DEBUG enabled, the function will do even more verifications, to help the user find any issues with the mbuf configuration. Fixes: b3fc5a1ae10d ("net/ena: add Tx preparation") Cc: stable@dpdk.org Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shai Brandes --- drivers/net/ena/ena_ethdev.c | 232 +++++++++++++++++++++++++++-------- drivers/net/ena/ena_ethdev.h | 5 +- 2 files changed, 185 insertions(+), 52 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 408e12751..a00d29aa1 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -147,6 +147,23 @@ static const struct ena_stats ena_stats_rx_strings[] = { #define ENA_TX_OFFLOAD_NOTSUP_MASK \ (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) +/** HW specific offloads capabilities. */ +/* IPv4 checksum offload. */ +#define ENA_L3_IPV4_CSUM 0x0001 +/* TCP/UDP checksum offload for IPv4 packets. */ +#define ENA_L4_IPV4_CSUM 0x0002 +/* TCP/UDP checksum offload for IPv4 packets with pseudo header checksum. */ +#define ENA_L4_IPV4_CSUM_PARTIAL 0x0004 +/* TCP/UDP checksum offload for IPv6 packets. */ +#define ENA_L4_IPV6_CSUM 0x0008 +/* TCP/UDP checksum offload for IPv6 packets with pseudo header checksum. */ +#define ENA_L4_IPV6_CSUM_PARTIAL 0x0010 +/* TSO support for IPv4 packets. */ +#define ENA_IPV4_TSO 0x0020 + +/* Device supports setting RSS hash. */ +#define ENA_RX_RSS_HASH 0x0040 + int ena_logtype_init; int ena_logtype_driver; @@ -1671,6 +1688,50 @@ static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev, return io_queue_num; } +static void +ena_set_offloads(struct ena_offloads *offloads, + struct ena_admin_feature_offload_desc *offload_desc) +{ + if (offload_desc->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) + offloads->tx_offloads |= ENA_IPV4_TSO; + + /* Tx IPv4 checksum offloads */ + if (offload_desc->tx & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK) + offloads->tx_offloads |= ENA_L3_IPV4_CSUM; + if (offload_desc->tx & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) + offloads->tx_offloads |= ENA_L4_IPV4_CSUM; + if (offload_desc->tx & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) + offloads->tx_offloads |= ENA_L4_IPV4_CSUM_PARTIAL; + + /* Tx IPv6 checksum offloads */ + if (offload_desc->tx & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) + offloads->tx_offloads |= ENA_L4_IPV6_CSUM; + if (offload_desc->tx & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) + offloads->tx_offloads |= ENA_L4_IPV6_CSUM_PARTIAL; + + /* Rx IPv4 checksum offloads */ + if (offload_desc->rx_supported & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK) + offloads->rx_offloads |= ENA_L3_IPV4_CSUM; + if (offload_desc->rx_supported & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) + offloads->rx_offloads |= ENA_L4_IPV4_CSUM; + + /* Rx IPv6 checksum offloads */ + if (offload_desc->rx_supported & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) + offloads->rx_offloads |= ENA_L4_IPV6_CSUM; + + if (offload_desc->rx_supported & + ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) + offloads->rx_offloads |= ENA_RX_RSS_HASH; +} + static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) { struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; @@ -1775,14 +1836,7 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) /* Set max MTU for this device */ adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; - /* set device support for offloads */ - adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx & - ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0; - adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx & - ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0; - adapter->offloads.rx_csum_supported = - (get_feat_ctx.offload.rx_supported & - ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0; + ena_set_offloads(&adapter->offloads, &get_feat_ctx.offload); /* Copy MAC address and point DPDK to it */ eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr; @@ -1936,24 +1990,29 @@ static int ena_infos_get(struct rte_eth_dev *dev, ETH_LINK_SPEED_100G; /* Set Tx & Rx features available for device */ - if (adapter->offloads.tso4_supported) + if (adapter->offloads.tx_offloads & ENA_IPV4_TSO) tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; - if (adapter->offloads.tx_csum_supported) - tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | - DEV_TX_OFFLOAD_UDP_CKSUM | - DEV_TX_OFFLOAD_TCP_CKSUM; + if (adapter->offloads.tx_offloads & ENA_L3_IPV4_CSUM) + tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM; + if (adapter->offloads.tx_offloads & + (ENA_L4_IPV4_CSUM_PARTIAL | ENA_L4_IPV4_CSUM | + ENA_L4_IPV6_CSUM | ENA_L4_IPV6_CSUM_PARTIAL)) + tx_feat |= DEV_TX_OFFLOAD_UDP_CKSUM | DEV_TX_OFFLOAD_TCP_CKSUM; - if (adapter->offloads.rx_csum_supported) - rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | - DEV_RX_OFFLOAD_UDP_CKSUM | - DEV_RX_OFFLOAD_TCP_CKSUM; + if (adapter->offloads.rx_offloads & ENA_L3_IPV4_CSUM) + rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM; + if (adapter->offloads.rx_offloads & + (ENA_L4_IPV4_CSUM | ENA_L4_IPV6_CSUM)) + rx_feat |= DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM; rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; tx_feat |= DEV_TX_OFFLOAD_MULTI_SEGS; /* Inform framework about available features */ dev_info->rx_offload_capa = rx_feat; + if (adapter->offloads.rx_offloads & ENA_RX_RSS_HASH) + dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_RSS_HASH; dev_info->rx_queue_offload_capa = rx_feat; dev_info->tx_offload_capa = tx_feat; dev_info->tx_queue_offload_capa = tx_feat; @@ -2114,45 +2173,60 @@ eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint32_t i; struct rte_mbuf *m; struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); + struct ena_adapter *adapter = tx_ring->adapter; struct rte_ipv4_hdr *ip_hdr; uint64_t ol_flags; + uint64_t l4_csum_flag; + uint64_t dev_offload_capa; uint16_t frag_field; + bool need_pseudo_csum; + dev_offload_capa = adapter->offloads.tx_offloads; for (i = 0; i != nb_pkts; i++) { m = tx_pkts[i]; ol_flags = m->ol_flags; - if (!(ol_flags & PKT_TX_IPV4)) + /* Check if any offload flag was set */ + if (ol_flags == 0) continue; - /* If there was not L2 header length specified, assume it is - * length of the ethernet header. - */ - if (unlikely(m->l2_len == 0)) - m->l2_len = sizeof(struct rte_ether_hdr); - - ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, - m->l2_len); - frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); - - if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) { - m->packet_type |= RTE_PTYPE_L4_NONFRAG; - - /* If IPv4 header has DF flag enabled and TSO support is - * disabled, partial chcecksum should not be calculated. - */ - if (!tx_ring->adapter->offloads.tso4_supported) - continue; - } - - if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || - (ol_flags & PKT_TX_L4_MASK) == - PKT_TX_SCTP_CKSUM) { + l4_csum_flag = ol_flags & PKT_TX_L4_MASK; + /* SCTP checksum offload is not supported by the ENA. */ + if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) || + l4_csum_flag == PKT_TX_SCTP_CKSUM) { + PMD_TX_LOG(DEBUG, + "mbuf[%" PRIu32 "] has unsupported offloads flags set: 0x%" PRIu64 "\n", + i, ol_flags); rte_errno = ENOTSUP; return i; } #ifdef RTE_LIBRTE_ETHDEV_DEBUG + /* Check if requested offload is also enabled for the queue */ + if ((ol_flags & PKT_TX_IP_CKSUM && + !(tx_ring->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) || + (l4_csum_flag == PKT_TX_TCP_CKSUM && + !(tx_ring->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) || + (l4_csum_flag == PKT_TX_UDP_CKSUM && + !(tx_ring->offloads & DEV_TX_OFFLOAD_UDP_CKSUM))) { + PMD_TX_LOG(DEBUG, + "mbuf[%" PRIu32 "]: requested offloads: %" PRIu16 " are not enabled for the queue[%u]\n", + i, m->nb_segs, tx_ring->id); + rte_errno = EINVAL; + return i; + } + + /* The caller is obligated to set l2 and l3 len if any cksum + * offload is enabled. + */ + if (unlikely(ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK) && + (m->l2_len == 0 || m->l3_len == 0))) { + PMD_TX_LOG(DEBUG, + "mbuf[%" PRIu32 "]: l2_len or l3_len values are 0 while the offload was requested\n", + i); + rte_errno = EINVAL; + return i; + } ret = rte_validate_tx_offload(m); if (ret != 0) { rte_errno = -ret; @@ -2160,16 +2234,76 @@ eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, } #endif - /* In case we are supposed to TSO and have DF not set (DF=0) - * hardware must be provided with partial checksum, otherwise - * it will take care of necessary calculations. + /* Verify HW support for requested offloads and determine if + * pseudo header checksum is needed. */ + need_pseudo_csum = false; + if (ol_flags & PKT_TX_IPV4) { + if (ol_flags & PKT_TX_IP_CKSUM && + !(dev_offload_capa & ENA_L3_IPV4_CSUM)) { + rte_errno = ENOTSUP; + return i; + } - ret = rte_net_intel_cksum_flags_prepare(m, - ol_flags & ~PKT_TX_TCP_SEG); - if (ret != 0) { - rte_errno = -ret; - return i; + if (ol_flags & PKT_TX_TCP_SEG && + !(dev_offload_capa & ENA_IPV4_TSO)) { + rte_errno = ENOTSUP; + return i; + } + + /* Check HW capabilities and if pseudo csum is needed + * for L4 offloads. + */ + if (l4_csum_flag != PKT_TX_L4_NO_CKSUM && + !(dev_offload_capa & ENA_L4_IPV4_CSUM)) { + if (dev_offload_capa & + ENA_L4_IPV4_CSUM_PARTIAL) { + need_pseudo_csum = true; + } else { + rte_errno = ENOTSUP; + return i; + } + } + + /* Parse the DF flag */ + ip_hdr = rte_pktmbuf_mtod_offset(m, + struct rte_ipv4_hdr *, m->l2_len); + frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); + if (frag_field & RTE_IPV4_HDR_DF_FLAG) { + m->packet_type |= RTE_PTYPE_L4_NONFRAG; + } else if (ol_flags & PKT_TX_TCP_SEG) { + /* In case we are supposed to TSO and have DF + * not set (DF=0) hardware must be provided with + * partial checksum. + */ + need_pseudo_csum = true; + } + } else if (ol_flags & PKT_TX_IPV6) { + /* There is no support for IPv6 TSO as for now. */ + if (ol_flags & PKT_TX_TCP_SEG) { + rte_errno = ENOTSUP; + return i; + } + + /* Check HW capabilities and if pseudo csum is needed */ + if (l4_csum_flag != PKT_TX_L4_NO_CKSUM && + !(dev_offload_capa & ENA_L4_IPV6_CSUM)) { + if (dev_offload_capa & + ENA_L4_IPV6_CSUM_PARTIAL) { + need_pseudo_csum = true; + } else { + rte_errno = ENOTSUP; + return i; + } + } + } + + if (need_pseudo_csum) { + ret = rte_net_intel_cksum_flags_prepare(m, ol_flags); + if (ret != 0) { + rte_errno = -ret; + return i; + } } } diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index af5eeea28..a5b41b30f 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -142,9 +142,8 @@ struct ena_stats_dev { }; struct ena_offloads { - bool tso4_supported; - bool tx_csum_supported; - bool rx_csum_supported; + uint32_t tx_offloads; + uint32_t rx_offloads; }; /* board specific private data structure */ -- 2.25.1