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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by CO1NAM11FT033.mail.protection.outlook.com (10.13.174.247) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4888.9 via Frontend Transport; Fri, 14 Jan 2022 10:52:39 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 14 Jan 2022 10:52:38 +0000 Received: from nvidia.com (10.127.8.11) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.986.9; Fri, 14 Jan 2022 02:52:36 -0800 From: Dmitry Kozlyuk To: CC: , Wang Yunjian , "Viacheslav Ovsiienko" , Matan Azrad Subject: [PATCH] common/mlx5: fix MR lookup for non-contiguous mempool Date: Fri, 14 Jan 2022 12:52:17 +0200 Message-ID: <20220114105217.343139-1-dkozlyuk@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.127.8.11] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: cec5c5dc-ec92-4cff-5813-08d9d74bfbbc X-MS-TrafficTypeDiagnostic: DM6PR12MB4763:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2958; 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SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(40470700002)(54906003)(2616005)(70586007)(70206006)(336012)(107886003)(6666004)(426003)(5660300002)(316002)(356005)(4326008)(81166007)(36860700001)(83380400001)(6286002)(40460700001)(186003)(16526019)(26005)(47076005)(86362001)(2906002)(55016003)(508600001)(1076003)(36756003)(8936002)(82310400004)(7696005)(6916009)(8676002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2022 10:52:39.4485 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cec5c5dc-ec92-4cff-5813-08d9d74bfbbc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4763 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Memory region (MR) lookup by address inside mempool MRs was not accounting for the upper bound of an MR. For mempools covered by multiple MRs this could return a wrong MR LKey, typically resulting in an unrecoverable TxQ failure: mlx5_net: Cannot change Tx QP state to INIT Invalid argument Corresponding message from /var/log/dpdk_mlx5_port_X_txq_Y_index_Z*: Unexpected CQE error syndrome 0x04 CQN = 128 SQN = 4848 wqe_counter = 0 wq_ci = 9 cq_ci = 122 This is likely to happen with --legacy-mem and IOVA-as-PA, because EAL intentionally maps pages at non-adjacent PA to non-adjacent VA in this mode, and MLX5 PMD works with VA. Fixes: 690b2a88c2f7 ("common/mlx5: add mempool registration facilities") Cc: stable@dpdk.org Reported-by: Wang Yunjian Signed-off-by: Dmitry Kozlyuk Reviewed-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_common_mr.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/common/mlx5/mlx5_common_mr.c b/drivers/common/mlx5/mlx5_common_mr.c index 1537b5d428..5f7e4f6734 100644 --- a/drivers/common/mlx5/mlx5_common_mr.c +++ b/drivers/common/mlx5/mlx5_common_mr.c @@ -1834,12 +1834,13 @@ mlx5_mempool_reg_addr2mr(struct mlx5_mempool_reg *mpr, uintptr_t addr, for (i = 0; i < mpr->mrs_n; i++) { const struct mlx5_pmd_mr *mr = &mpr->mrs[i].pmd_mr; - uintptr_t mr_addr = (uintptr_t)mr->addr; + uintptr_t mr_start = (uintptr_t)mr->addr; + uintptr_t mr_end = mr_start + mr->len; - if (mr_addr <= addr) { + if (mr_start <= addr && addr < mr_end) { lkey = rte_cpu_to_be_32(mr->lkey); - entry->start = mr_addr; - entry->end = mr_addr + mr->len; + entry->start = mr_start; + entry->end = mr_end; entry->lkey = lkey; break; } -- 2.25.1