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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.238) by CO1NAM11FT051.mail.protection.outlook.com (10.13.174.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4951.12 via Frontend Transport; Thu, 3 Feb 2022 08:47:16 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 3 Feb 2022 08:47:16 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Thu, 3 Feb 2022 00:47:14 -0800 From: Viacheslav Ovsiienko To: CC: , , , Subject: [PATCH v2 1/2] net/mlx5: fix metadata endianness in modify field action Date: Thu, 3 Feb 2022 10:46:51 +0200 Message-ID: <20220203084652.19167-1-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <49fa76c7-30fe-3128-81ac-38779f557f33@intel.com> References: <49fa76c7-30fe-3128-81ac-38779f557f33@intel.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6721de73-6f3d-4969-3c66-08d9e6f1c80b X-MS-TrafficTypeDiagnostic: CY4PR12MB1608:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; 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SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(6666004)(336012)(6286002)(36756003)(70586007)(16526019)(7696005)(2906002)(508600001)(82310400004)(81166007)(426003)(1076003)(2616005)(8676002)(54906003)(70206006)(55016003)(8936002)(26005)(6916009)(356005)(36860700001)(4326008)(186003)(316002)(47076005)(86362001)(5660300002)(83380400001)(40460700003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2022 08:47:16.6228 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6721de73-6f3d-4969-3c66-08d9e6f1c80b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT051.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1608 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org As modify field action immediate source parameter the metadata should follow the CPU endianness (according to SET_META action structure format), and mlx5 PMD wrongly handled the immediate parameter metadata buffer as big-endian, resulting in wrong metadata set action with incorrect endianness. Fixes: 40c8fb1fd3b3 ("net/mlx5: update modify field action") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_dv.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index af90a7fd0a..10ef2af06a 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1867,7 +1867,7 @@ flow_dv_convert_action_modify_field struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = { {0, 0, 0} }; uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0}; - uint32_t type; + uint32_t type, meta = 0; uint32_t shift = 0; if (conf->src.field == RTE_FLOW_FIELD_POINTER || @@ -1880,6 +1880,11 @@ flow_dv_convert_action_modify_field item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ? (void *)(uintptr_t)conf->src.pvalue : (void *)(uintptr_t)&conf->src.value; + if (conf->dst.field == RTE_FLOW_FIELD_META) { + meta = *(const unaligned_uint32_t *)item.spec; + meta = rte_cpu_to_be_32(meta); + item.spec = &meta; + } } else { type = MLX5_MODIFICATION_TYPE_COPY; /** For COPY fill the destination field (dcopy) without mask. */ -- 2.18.1