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Wed, 23 Feb 2022 05:48:41 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Subject: [PATCH v2 1/5] doc: remove obsolete explanations from mlx5 guide Date: Wed, 23 Feb 2022 15:48:30 +0200 Message-ID: <20220223134834.2840916-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223134834.2840916-1-michaelba@nvidia.com> References: <20220222124815.2587851-1-michaelba@nvidia.com> <20220223134834.2840916-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e6085122-5275-428f-b645-08d9f6d335ed X-MS-TrafficTypeDiagnostic: BYAPR12MB3383:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PF29s44vlWElb7mEPS7BZqt5DihyePU29PAOql+NMbERc8NXSbZdzWRNCca09GJR7cIDGFx0piQc7/jKFQ9ZPioeUgQaU/UtELnj2X1AJ3jeFUV3IU0xyCwzsxCPs6oDlDeqw6ZJecCuL2+/9pUHMbRWjgGX7HK5Le20eM+0SPx9Haw4uiqllBp4/6MttPSyBIEGJaiUAe3p0ekYQwJKkx6l1X66NwvzALvw776o7b875giVlA4POhLVGiDYa39CXWc1FscPJ/yWZaF8Uy5nlp85L7EntDdtXOUlE5QVOM30KZjKbq3X7KkZlznlQ862T6XcK/6pFJU5ju7M17z6qEz1HmSYnaamj4e9vdzqSHxivseJjNgHM8i2eKXSvQx6cwYeKODDiVtn1kmTkTHp+za+3qWK922LSEaxH3aKTDzXR66I2eFoa0rELglT0Dnx0skLhHFZ2ZFixqpI47BZFaMmsqcQHawCYumVtoDih848Qj0G0gUbA3FF5tipdXu3m6ev29ScPtpNbzZ1ZpJqXoMKiYOlcO7iahG31C1EY1qBCDlrfE61yUoHMdmdeCE5z8Zhq5crqk4izM6w6glgC7nFoWxS6rPnTKPCrkAlpWWJyxFGVhyd7UfQm82Vw+fdIpxJzsBQ0R4t6KVtBsCZD+gGxDPCaEPFgJQUN/4peC1g28dLdYDyuMiwgqtpqBey5gsZGn7b849Js5opFR3+Jg== X-Forefront-Antispam-Report: CIP:12.22.5.236; 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However, more updating should have been done. In environment variables doc, there was explanation according to vectorized Tx which isn't relevant anymore. This patch removes this irrelevant explanation. Fixes: a6bd4911ad93 ("net/mlx5: remove Tx implementation") Cc: stable@dpdk.org Signed-off-by: Michael Baum Reviewed-by: Raslan Darawsheh Acked-by: Viacheslav Ovsiienko --- doc/guides/nics/mlx5.rst | 9 --------- 1 file changed, 9 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 6494f4ae39..c21df81717 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -557,15 +557,6 @@ Environment variables The register would be flushed to HW usually when the write-combining buffer becomes full, but it depends on CPU design. - Except for vectorized Tx burst routines, a write memory barrier is enforced - after updating the register so that the update can be immediately visible to - HW. - - When vectorized Tx burst is called, the barrier is set only if the burst size - is not aligned to MLX5_VPMD_TX_MAX_BURST. However, setting this environmental - variable will bring better latency even though the maximum throughput can - slightly decline. - Run-time configuration ~~~~~~~~~~~~~~~~~~~~~~ -- 2.25.1