patch 'net/iavf: count continuous DD bits for Arm' has been queued to stable release 19.11.12

[christian.ehrhardt@canonical.com]

Hi,

FYI, your patch has been queued to stable release 19.11.12

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 02/27/22. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/cpaelzer/dpdk-stable-queue

This queued commit can be viewed at:
https://github.com/cpaelzer/dpdk-stable-queue/commit/55f2ea35c7cafdb178e59862d66eaf73b3282706

Thanks.

Christian Ehrhardt <christian.ehrhardt@canonical.com>

---
From 55f2ea35c7cafdb178e59862d66eaf73b3282706 Mon Sep 17 00:00:00 2001
From: Kathleen Capella <kathleen.capella@arm.com>
Date: Sat, 5 Feb 2022 00:26:29 +0000
Subject: [PATCH] net/iavf: count continuous DD bits for Arm

[ upstream commit 3d88d5e401f6d04882415866012a98bced0c3cb8 ]

On Arm platforms, reading of descriptors may be re-ordered causing the
status of DD bits to be discontinuous. Add logic to only process
continuous descriptors by checking DD bits.

Fixes: 1060591eada5 ("net/avf: enable bulk allocate Rx")

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/iavf/iavf_rxtx.c | 26 ++++++++++++++++++++++----
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c
index bc67712d9c..d406f0d992 100644
--- a/drivers/net/iavf/iavf_rxtx.c
+++ b/drivers/net/iavf/iavf_rxtx.c
@@ -1101,7 +1101,7 @@ iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
 	uint16_t pkt_len;
 	uint64_t qword1;
 	uint32_t rx_status;
-	int32_t s[IAVF_LOOK_AHEAD], nb_dd;
+	int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
 	int32_t i, j, nb_rx = 0;
 	uint64_t pkt_flags;
 	static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
@@ -1150,9 +1150,27 @@ iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
 
 		rte_smp_rmb();
 
-		/* Compute how many status bits were set */
-		for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
-			nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
+		/* Compute how many contiguous DD bits were set */
+		for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
+			var = s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
+#ifdef RTE_ARCH_ARM
+			/* For Arm platforms, count only contiguous descriptors
+			 * whose DD bit is set to 1. On Arm platforms, reads of
+			 * descriptors can be reordered. Since the CPU may
+			 * be reading the descriptors as the NIC updates them
+			 * in memory, it is possbile that the DD bit for a
+			 * descriptor earlier in the queue is read as not set
+			 * while the DD bit for a descriptor later in the queue
+			 * is read as set.
+			 */
+			if (var)
+				nb_dd += 1;
+			else
+				break;
+#else
+			nb_dd += var;
+#endif
+		}
 
 		nb_rx += nb_dd;
 
-- 
2.35.0

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2022-02-25 16:58:46.315135552 +0100
+++ 0054-net-iavf-count-continuous-DD-bits-for-Arm.patch	2022-02-25 16:58:44.300990467 +0100
@@ -1 +1 @@
-From 3d88d5e401f6d04882415866012a98bced0c3cb8 Mon Sep 17 00:00:00 2001
+From 55f2ea35c7cafdb178e59862d66eaf73b3282706 Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit 3d88d5e401f6d04882415866012a98bced0c3cb8 ]
+
@@ -11 +12,0 @@
-Cc: stable@dpdk.org
@@ -21 +22 @@
-index 7158938643..f07d886821 100644
+index bc67712d9c..d406f0d992 100644
@@ -24 +25 @@
-@@ -1897,7 +1897,7 @@ iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
+@@ -1101,7 +1101,7 @@ iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
@@ -32,2 +33,2 @@
- 	const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
-@@ -1928,9 +1928,27 @@ iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
+ 	static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
+@@ -1150,9 +1150,27 @@ iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)