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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by BN8NAM11FT018.mail.protection.outlook.com (10.13.176.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5017.22 via Frontend Transport; Sun, 27 Feb 2022 14:01:31 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 27 Feb 2022 14:01:05 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Sun, 27 Feb 2022 06:01:03 -0800 From: Raja Zidane To: CC: , Subject: [PATCH V2] compress/mlx5: support out-of-space status Date: Sun, 27 Feb 2022 16:00:52 +0200 Message-ID: <20220227140052.13212-1-rzidane@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220223133142.13407-1-rzidane@nvidia.com> References: <20220223133142.13407-1-rzidane@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f5f1fb5e-0994-4c5e-8543-08d9f9f9a88e X-MS-TrafficTypeDiagnostic: CH2PR12MB4119:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Feb 2022 14:01:31.8002 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5f1fb5e-0994-4c5e-8543-08d9f9f9a88e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4119 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org When trying to dequeue, an OP may fail due to insufficient space for the OP output, the compressdev API defines out-of-space for OP status. The driver can detect out-of-space errors and report them to the user. Check if hw_error_syndrome specifies out-of-space and set the OP status accordingly. Also added an error message for a case of missing B-final flag. Fixes: f8c97babc9f4 ("compress/mlx5: add data-path functions") Cc: stable@dpdk.org Signed-off-by: Raja Zidane --- Acked-by: Matan Azrad V2: fix implicit switch-case fallthrough drivers/common/mlx5/mlx5_prm.h | 5 +++++ drivers/compress/mlx5/mlx5_compress.c | 13 ++++++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index ce3e47059f..44b18225f6 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -262,6 +262,9 @@ /* Maximum number of DS in WQE. Limited by 6-bit field. */ #define MLX5_DSEG_MAX 63 +/* The 32 bit syndrome offset in struct mlx5_err_cqe. */ +#define MLX5_ERROR_CQE_SYNDROME_OFFSET 52 + /* The completion mode offset in the WQE control segment line 2. */ #define MLX5_COMP_MODE_OFFSET 2 @@ -581,6 +584,8 @@ struct mlx5_rdma_write_wqe { #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u +#define MLX5_GGA_COMP_OUT_OF_SPACE_SYNDROME_BE 0x29D0084 +#define MLX5_GGA_COMP_MISSING_BFINAL_SYNDROME_BE 0x29D0011 struct mlx5_wqe_metadata_seg { uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */ diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 7a482c3fbb..d64a628c74 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -562,7 +562,18 @@ mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp, qp->qp.wqes; volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr; - op->status = RTE_COMP_OP_STATUS_ERROR; + volatile uint32_t *synd_word = RTE_PTR_ADD(cqe, MLX5_ERROR_CQE_SYNDROME_OFFSET); + switch (*synd_word) { + case MLX5_GGA_COMP_OUT_OF_SPACE_SYNDROME_BE: + op->status = RTE_COMP_OP_STATUS_OUT_OF_SPACE_TERMINATED; + DRV_LOG(DEBUG, "OUT OF SPACE error, output is bigger than dst buffer."); + break; + case MLX5_GGA_COMP_MISSING_BFINAL_SYNDROME_BE: + DRV_LOG(DEBUG, "The last compressed block missed the B-final flag; maybe the compressed data is not complete or garbaged?"); + /* fallthrough */ + default: + op->status = RTE_COMP_OP_STATUS_ERROR; + } op->consumed = 0; op->produced = 0; op->output_chksum = 0; -- 2.21.0