patch 'doc: remove obsolete vector Tx explanations from mlx5 guide' has been queued to stable release 21.11.1

[Kevin Traynor <ktraynor@redhat.com>]

Hi,

FYI, your patch has been queued to stable release 21.11.1

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 03/06/22. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/kevintraynor/dpdk-stable

This queued commit can be viewed at:
https://github.com/kevintraynor/dpdk-stable/commit/97cf74ba16c0865564b3f19ce273fd19b6bcb411

Thanks.

Kevin

---
From 97cf74ba16c0865564b3f19ce273fd19b6bcb411 Mon Sep 17 00:00:00 2001
From: Michael Baum <michaelba@nvidia.com>
Date: Wed, 23 Feb 2022 15:48:30 +0200
Subject: [PATCH] doc: remove obsolete vector Tx explanations from mlx5 guide

[ upstream commit 9c7dc70265696ef402ed6f54a2552ed7684560aa ]

Vectorized routines were removed in result of Tx datapath refactoring,
and devarg keys documentation was updated.

However, more updating should have been done. In environment variables
doc, there was explanation according to vectorized Tx which isn't
relevant anymore.

This patch removes this irrelevant explanation.

Fixes: a6bd4911ad93 ("net/mlx5: remove Tx implementation")

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Reviewed-by: Raslan Darawsheh <rasland@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 doc/guides/nics/mlx5.rst | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index daa7f2affb..002c89e9bc 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -555,13 +555,4 @@ Environment variables
   becomes full, but it depends on CPU design.
 
-  Except for vectorized Tx burst routines, a write memory barrier is enforced
-  after updating the register so that the update can be immediately visible to
-  HW.
-
-  When vectorized Tx burst is called, the barrier is set only if the burst size
-  is not aligned to MLX5_VPMD_TX_MAX_BURST. However, setting this environmental
-  variable will bring better latency even though the maximum throughput can
-  slightly decline.
-
 Run-time configuration
 ~~~~~~~~~~~~~~~~~~~~~~
-- 
2.34.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2022-03-01 10:41:03.785573139 +0000
+++ 0085-doc-remove-obsolete-vector-Tx-explanations-from-mlx5.patch	2022-03-01 10:41:01.450244128 +0000
@@ -1 +1 @@
-From 9c7dc70265696ef402ed6f54a2552ed7684560aa Mon Sep 17 00:00:00 2001
+From 97cf74ba16c0865564b3f19ce273fd19b6bcb411 Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit 9c7dc70265696ef402ed6f54a2552ed7684560aa ]
+
@@ -16 +17,0 @@
-Cc: stable@dpdk.org
@@ -26 +27 @@
-index c3cc0c0f41..3f5c8bb303 100644
+index daa7f2affb..002c89e9bc 100644
@@ -29 +30 @@
-@@ -558,13 +558,4 @@ Environment variables
+@@ -555,13 +555,4 @@ Environment variables