From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ED5ECA0093 for ; Wed, 9 Mar 2022 12:52:38 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C89A640395; Wed, 9 Mar 2022 12:52:38 +0100 (CET) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2064.outbound.protection.outlook.com [40.107.244.64]) by mails.dpdk.org (Postfix) with ESMTP id 9F58940395 for ; Wed, 9 Mar 2022 12:52:37 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XALHN34QyqVRrzHVv7MUNGtOfYs8OuYIQS38ILWtfx3NF/0zutzrOL9ezWKd2WeSIWWn3qi1GdXPW0C1xdXa4ufBjn5zHtbG+e5mx6mRzhYgXXLwSCtE5En1W3BxKENIZjUAVHmYUcVFGj6hgO5JQQyS8dt+U+Jd5Chf/3gs8k3H/l22CN1ESX87dpQtIA2JUSqwqdXe2KQsfvwbRA+REofjUWoILtVR6uKWg2PEp6g+E+34TOqdYaA7NHMP2J9xO/iq/+S/WxRF8I4MVM7yIRpm1bPKH6jMguTlEfX6nyDnYhrXzk1xnsBf+5Hi3T5LVpiRrYLlqiZJ8bBL12SjBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=LVOn4fOZxMlyQJvU9HN1g5SvBx0nv/r0CKPeOV1+YM0=; b=U6mrCCTbQywtnDR/nSqNL3BIyNxgU6KQTn2DYF5wYZezU0+L9CG6gJH5lzLDJ/u5NuVimtNxkeRr192MIkcrCR5AnXYxg6pIn/qrgv9xxsypZsXiW5YnY02GALYZfhoFZKBoQZhdLjloD50K+GFPEqO4CpDJc/DVKLsZB5N+qoYs7ZgeIVJ2/uyIkw2Tx1aqIVW5r3F5l8XI1rfhVfevxORdwl3i2txtwCAa4FGEw18n/2K4tA/OV2Xh1SflM/7wY0/Pf8GntymNYhThHWizzXEC1Tb/P0pQnF0tOCkHjK1vlkFptA5Rj8UTqj4Lg65JaPqMV5e4xqV0D1ZTolwlww== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LVOn4fOZxMlyQJvU9HN1g5SvBx0nv/r0CKPeOV1+YM0=; b=fIYhi4PtIwEcWi1plgp33AmO2L1vzAR4NzpZbcXUOJOmmE3Z9vyaqc8HcFa3mhAdR63wq3htxo65RFfmWKJJ+JwadhjA1DCJIny4iMn0hAI7HmpguYs6h4rChrdoJh3j25X1yMHPISGgTZMux088GAB5IpgUD5157Q+6uaJgVUF1QXrWui7m0uygvwIaKtErTnyH0cGvZB7XXyP9JQPRztBQ7D0CdikIKf/XyryCuVAE+h9oBatnIfrMSZkrAc1Yx+GUghTfBEG5LIbz97e9hWdeRWOVpAB5fj0FKPQJ7yA7BXEnvbdDtZHDIaVitY3FsLeOnABU/8iwQOEiUgbfYQ== Received: from MW4PR03CA0203.namprd03.prod.outlook.com (2603:10b6:303:b8::28) by CH2PR12MB4136.namprd12.prod.outlook.com (2603:10b6:610:a4::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5038.14; Wed, 9 Mar 2022 11:52:35 +0000 Received: from CO1NAM11FT033.eop-nam11.prod.protection.outlook.com (2603:10b6:303:b8:cafe::5c) by MW4PR03CA0203.outlook.office365.com (2603:10b6:303:b8::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5038.15 via Frontend Transport; Wed, 9 Mar 2022 11:52:35 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by CO1NAM11FT033.mail.protection.outlook.com (10.13.174.247) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5038.14 via Frontend Transport; Wed, 9 Mar 2022 11:52:35 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 9 Mar 2022 11:52:34 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Wed, 9 Mar 2022 03:52:29 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9 via Frontend Transport; Wed, 9 Mar 2022 03:52:28 -0800 From: Michael Baum To: CC: Matan Azrad , Viacheslav Ovsiienko , Xueming Li Subject: [PATCH 20.11] net/mlx5: workaround ASO memory region creation Date: Wed, 9 Mar 2022 13:52:24 +0200 Message-ID: <20220309115224.820658-1-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5c727fb2-a52d-4579-0cf2-08da01c34d2d X-MS-TrafficTypeDiagnostic: CH2PR12MB4136:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4E1CReF4Q9dYiwUMyzsKJdqUsenx5sGTrRVfgDd6npVWiZKGV8BnuPK7eIWQezm1cutDs1g/W+DbM1gvjdcHMOQPbiBYMyMfndBA79BKnUqkhHZ1u2e7e0n/O3wAcdMyLDoqu6fTPCmb31KwM6vMMrLcoqTHpg2CXQTpb/xuF+AAtBioRrGWysRxBkoCK+P+c8gzv2vxmyRPK/YvpYQimgV7BFx2cT1YBDTW4Ty+JDLGQMuVKqxs3eRfUxV19/0wjuOmxVugoJGukmpF4R1+UV86DksC1PsQHvP3OKag+Nl0uwwMvtRcF8t5M43yTfGYXSjDmOB9yDFrUphzzn5oM3BizKDD8aY1NxqaSVPwxfxOFWL4XEHWVaiyTQ/D9tMoqc1nAqiTO5Qw1kFU50Qce+sHRrAk5FYoaqaqEW0Y9DfQmcoqcG26fMwgK3g94X63hTlY+7E++9lnLvuDWOFTmnhn1gQYy+XElmE8LWmtVmJuFLu48bllH4GrrJi3dmm+4ZkzmkfVV8UygF2E9Jw8cbKXUp+ZNs2f0z5JIFGQRJyU9KKg8r1/aryFmN9bjZHqSQwXy18DrKX7jeROTTu6gSJutLXdSzxnKwD0sDBFKb5A5mzLfkKZxoZG2jVukJJgOxStuwRolk/JUGqnCxedUlXgV7eT5sxPiebTHiTBwVmQulPBeS4Ev+nXoa4HOq04jcn8bGt/do8R+J6I851TDQ== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(82310400004)(36860700001)(47076005)(86362001)(4326008)(26005)(508600001)(70586007)(70206006)(6916009)(6286002)(6666004)(83380400001)(7696005)(2906002)(336012)(426003)(36756003)(5660300002)(55016003)(8936002)(40460700003)(54906003)(356005)(1076003)(107886003)(81166007)(2616005)(316002)(186003)(8676002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2022 11:52:35.0301 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c727fb2-a52d-4579-0cf2-08da01c34d2d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4136 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org [ upstream commit cd414f81d1afdabf5cf13a1d9e859877af176ab9 ] Due to kernel issue in direct MKEY creation using the DevX API for physical memory, this patch replaces the ASO MR creation to use Verbs API. Fixes: f935ed4b645a ("net/mlx5: support flow hit action for aging") Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/common/mlx5/linux/mlx5_common_verbs.c | 1 - drivers/net/mlx5/mlx5.h | 10 +- drivers/net/mlx5/mlx5_flow_age.c | 97 ++++++++----------- 3 files changed, 41 insertions(+), 67 deletions(-) diff --git a/drivers/common/mlx5/linux/mlx5_common_verbs.c b/drivers/common/mlx5/linux/mlx5_common_verbs.c index 339535dd04..aa560f05f2 100644 --- a/drivers/common/mlx5/linux/mlx5_common_verbs.c +++ b/drivers/common/mlx5/linux/mlx5_common_verbs.c @@ -37,7 +37,6 @@ mlx5_common_verbs_reg_mr(void *pd, void *addr, size_t length, { struct ibv_mr *ibv_mr; - memset(pmd_mr, 0, sizeof(*pmd_mr)); ibv_mr = mlx5_glue->reg_mr(pd, addr, length, IBV_ACCESS_LOCAL_WRITE | (haswell_broadwell_cpu ? 0 : diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index d5016545b0..00713d6647 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -479,14 +479,6 @@ struct mlx5_aso_cq { uint64_t errors; }; -struct mlx5_aso_devx_mr { - void *buf; - uint64_t length; - struct mlx5dv_devx_umem *umem; - struct mlx5_devx_obj *mkey; - bool is_indirect; -}; - struct mlx5_aso_sq_elem { struct mlx5_aso_age_pool *pool; uint16_t burst_size; @@ -503,7 +495,7 @@ struct mlx5_aso_sq { }; volatile uint32_t *db_rec; volatile uint64_t *uar_addr; - struct mlx5_aso_devx_mr mr; + struct mlx5_pmd_mr mr; uint16_t pi; uint32_t head; uint32_t tail; diff --git a/drivers/net/mlx5/mlx5_flow_age.c b/drivers/net/mlx5/mlx5_flow_age.c index aae7a3758a..e110288c85 100644 --- a/drivers/net/mlx5/mlx5_flow_age.c +++ b/drivers/net/mlx5/mlx5_flow_age.c @@ -99,84 +99,65 @@ mlx5_aso_cq_create(void *ctx, struct mlx5_aso_cq *cq, uint16_t log_desc_n, /** * Free MR resources. * + * @param[in] sh + * Pointer to shared device context. * @param[in] mr * MR to free. */ static void -mlx5_aso_devx_dereg_mr(struct mlx5_aso_devx_mr *mr) +mlx5_aso_dereg_mr(struct mlx5_dev_ctx_shared *sh, struct mlx5_pmd_mr *mr) { - claim_zero(mlx5_devx_cmd_destroy(mr->mkey)); - if (!mr->is_indirect && mr->umem) - claim_zero(mlx5_glue->devx_umem_dereg(mr->umem)); - mlx5_free(mr->buf); + void *addr = mr->addr; + + sh->share_cache.dereg_mr_cb(mr); + mlx5_free(addr); memset(mr, 0, sizeof(*mr)); } /** * Register Memory Region. * - * @param[in] ctx - * Context returned from mlx5 open_device() glue function. + * @param[in] sh + * Pointer to shared device context. * @param[in] length * Size of MR buffer. * @param[in/out] mr * Pointer to MR to create. - * @param[in] pdn - * Protection Domain number to use. * * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ static int -mlx5_aso_devx_reg_mr(void *ctx, size_t length, struct mlx5_aso_devx_mr *mr, - int pdn) +mlx5_aso_reg_mr(struct mlx5_dev_ctx_shared *sh, size_t length, + struct mlx5_pmd_mr *mr) { - struct mlx5_devx_mkey_attr mkey_attr; + int ret; - mr->buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, length, 4096, - SOCKET_ID_ANY); - if (!mr->buf) { - DRV_LOG(ERR, "Failed to create ASO bits mem for MR by Devx."); + mr->addr = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, length, 4096, + SOCKET_ID_ANY); + if (!mr->addr) { + DRV_LOG(ERR, "Failed to create ASO bits mem for MR."); return -1; } - mr->umem = mlx5_glue->devx_umem_reg(ctx, mr->buf, length, - IBV_ACCESS_LOCAL_WRITE); - if (!mr->umem) { - DRV_LOG(ERR, "Failed to register Umem for MR by Devx."); - goto error; - } - mkey_attr.addr = (uintptr_t)mr->buf; - mkey_attr.size = length; - mkey_attr.umem_id = mlx5_os_get_umem_id(mr->umem); - mkey_attr.pd = pdn; - mkey_attr.pg_access = 1; - mkey_attr.klm_array = NULL; - mkey_attr.klm_num = 0; - mkey_attr.relaxed_ordering_read = 0; - mkey_attr.relaxed_ordering_write = 0; - mr->mkey = mlx5_devx_cmd_mkey_create(ctx, &mkey_attr); - if (!mr->mkey) { + ret = sh->share_cache.reg_mr_cb(sh->pd, mr->addr, length, mr); + if (ret) { DRV_LOG(ERR, "Failed to create direct Mkey."); - goto error; + mlx5_free(mr->addr); + return -1; } - mr->length = length; - mr->is_indirect = false; return 0; -error: - if (mr->umem) - claim_zero(mlx5_glue->devx_umem_dereg(mr->umem)); - mlx5_free(mr->buf); - return -1; } /** * Destroy Send Queue used for ASO access. * + * @param[in] sh + * Pointer to shared device context. * @param[in] sq * ASO SQ to destroy. */ static void -mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq) +mlx5_aso_destroy_sq(struct mlx5_dev_ctx_shared *sh, struct mlx5_aso_sq *sq) { if (sq->wqe_umem) { mlx5_glue->devx_umem_dereg(sq->wqe_umem); @@ -192,7 +173,7 @@ mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq) } if (sq->cq.cq) mlx5_aso_cq_destroy(&sq->cq); - mlx5_aso_devx_dereg_mr(&sq->mr); + mlx5_aso_dereg_mr(sh, &sq->mr); memset(sq, 0, sizeof(*sq)); } @@ -214,8 +195,8 @@ mlx5_aso_init_sq(struct mlx5_aso_sq *sq) for (i = 0, wqe = &sq->wqes[0]; i < size; ++i, ++wqe) { wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) | (sizeof(*wqe) >> 4)); - wqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.mkey->id); - addr = (uint64_t)((uint64_t *)sq->mr.buf + i * + wqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.lkey); + addr = (uint64_t)((uint64_t *)sq->mr.addr + i * MLX5_ASO_AGE_ACTIONS_PER_POOL / 64); wqe->aso_cseg.va_h = rte_cpu_to_be_32((uint32_t)(addr >> 32)); wqe->aso_cseg.va_l_r = rte_cpu_to_be_32((uint32_t)addr | 1u); @@ -232,8 +213,8 @@ mlx5_aso_init_sq(struct mlx5_aso_sq *sq) /** * Create Send Queue used for ASO access. * - * @param[in] ctx - * Context returned from mlx5 open_device() glue function. + * @param[in] sh + * Pointer to shared device context. * @param[in/out] sq * Pointer to SQ to create. * @param[in] uar @@ -244,12 +225,14 @@ mlx5_aso_init_sq(struct mlx5_aso_sq *sq) * EQ number. * @param[in] log_desc_n * Log of number of descriptors in queue. + * @param[in] ts_format + * timestamp format supported by the queue. * * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ static int -mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, +mlx5_aso_sq_create(struct mlx5_dev_ctx_shared *sh, struct mlx5_aso_sq *sq, struct mlx5dv_devx_uar *uar, uint32_t pdn, uint32_t eqn, uint16_t log_desc_n, uint32_t ts_format) { @@ -261,10 +244,10 @@ mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, uint32_t wq_size = sizeof(struct mlx5_aso_wqe) * sq_desc_n; int ret; - if (mlx5_aso_devx_reg_mr(ctx, (MLX5_ASO_AGE_ACTIONS_PER_POOL / 8) * - sq_desc_n, &sq->mr, pdn)) + if (mlx5_aso_reg_mr(sh, (MLX5_ASO_AGE_ACTIONS_PER_POOL / 8) * sq_desc_n, + &sq->mr)) return -1; - if (mlx5_aso_cq_create(ctx, &sq->cq, log_desc_n, + if (mlx5_aso_cq_create(sh->ctx, &sq->cq, log_desc_n, mlx5_os_get_devx_uar_page_id(uar), eqn)) goto error; sq->log_desc_n = log_desc_n; @@ -276,7 +259,7 @@ mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, rte_errno = ENOMEM; goto error; } - sq->wqe_umem = mlx5_glue->devx_umem_reg(ctx, + sq->wqe_umem = mlx5_glue->devx_umem_reg(sh->ctx, (void *)(uintptr_t)sq->umem_buf, wq_size + sizeof(*sq->db_rec) * 2, @@ -304,7 +287,7 @@ mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, wq_attr->dbr_umem_id = wq_attr->wq_umem_id; wq_attr->dbr_addr = wq_size; wq_attr->dbr_umem_valid = 1; - sq->sq = mlx5_devx_cmd_create_sq(ctx, &attr); + sq->sq = mlx5_devx_cmd_create_sq(sh->ctx, &attr); if (!sq->sq) { DRV_LOG(ERR, "Can't create sq object."); rte_errno = ENOMEM; @@ -326,7 +309,7 @@ mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, mlx5_aso_init_sq(sq); return 0; error: - mlx5_aso_destroy_sq(sq); + mlx5_aso_destroy_sq(sh, sq); return -1; } @@ -342,7 +325,7 @@ mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh) { - return mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, + return mlx5_aso_sq_create(sh, &sh->aso_age_mng->aso_sq, sh->tx_uar, sh->pdn, sh->eqn, MLX5_ASO_QUEUE_LOG_DESC, sh->sq_ts_format); } @@ -356,7 +339,7 @@ mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh) void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh) { - mlx5_aso_destroy_sq(&sh->aso_age_mng->aso_sq); + mlx5_aso_destroy_sq(sh, &sh->aso_age_mng->aso_sq); } /** @@ -486,7 +469,7 @@ mlx5_aso_age_action_update(struct mlx5_dev_ctx_shared *sh, uint16_t n) uint16_t idx = (sq->tail + i) & mask; struct mlx5_aso_age_pool *pool = sq->elts[idx].pool; uint64_t diff = curr - pool->time_of_last_age_check; - uint64_t *addr = sq->mr.buf; + uint64_t *addr = sq->mr.addr; int j; addr += idx * MLX5_ASO_AGE_ACTIONS_PER_POOL / 64; -- 2.25.1