From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 93441A0093 for ; Wed, 9 Mar 2022 17:32:40 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8D89F4013F; Wed, 9 Mar 2022 17:32:40 +0100 (CET) Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mails.dpdk.org (Postfix) with ESMTP id 729B0410E6 for ; Wed, 9 Mar 2022 17:32:39 +0100 (CET) Received: by mail-wm1-f43.google.com with SMTP id n33-20020a05600c3ba100b003832caf7f3aso3221453wms.0 for ; Wed, 09 Mar 2022 08:32:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a+/DF4qIxm2vnKd4M5DT0xnguryAASva720G8dB3b74=; b=QOkL00jJO085O9ggK6o8xGeuPL1eD+jLB70/PSzW0ZuwMaRvmnbKhXB+J3EkK1rp4T 44sALzgntsXcEOrbE12TrPfjt0fgT1xNcHKsbgNYKOSS9iGwFkhPwcEuIp/tP3JBltwB w8uTmvcQ7NsnuqoPdp4qNf2UTiaf6JJHWxjijAS2oUMCKgtdZArCrkBXhqTj/ljv01YD YcJbQxS8fh1n4V2D3d1AwcVQA8bp8iustcLIZLaEyP+YUSWmM88gNktXOjUEuNFhwGmN K/ShghYRj+Kdi3dy1bSOSPZNAXv8bElu4YHPrgWqnnLIlr4L5b47rwAL/osrHx8sihsW AHug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a+/DF4qIxm2vnKd4M5DT0xnguryAASva720G8dB3b74=; b=Bh93zBpcJthivlcuOqV+TsAOedJbvIhXc/di1P4U8mvw8+9YEgLO+lE8uRma7j0DbS rDUMNoHW243DeOpETMF337WUtnzgf/uqIvf4hgLis/bx6n9G/jDicrrnhmmEL2mtqq6Y vTJElo/EENvdddh62xZPKrlBnGIRpAG2PKm2oe2GfzKNVNSLCobX3n40Q3rSPfsZHJ7C ijPPkg9wk2eK5xYwvWDwBdqpBZADJXpj9ebsm12m/HD2/RHlTW08BeF5r++/N15SVZxR YM8OXa9Y/G2kpMA59HJCxMjNPp6DlXlsJ3DHxXalbGTwYAGjkYbL2cUEC0TyuPluzdMs C/Ew== X-Gm-Message-State: AOAM530jc29IjMwMlXjlxL6qYkRZ2UQ8N/fRNkvTwZrcCntFkUDqurqT TD0s8rFL7TUKbVaawCb+pYWxwaZ7CaY= X-Google-Smtp-Source: ABdhPJyC33lkkXsicpAUzaV+sGQpYrv+ra1m+Vx3rC6nKViyZjzI76+txapoYCFOshQ+9O7/tO4cjQ== X-Received: by 2002:a7b:c4c7:0:b0:381:874e:30a9 with SMTP id g7-20020a7bc4c7000000b00381874e30a9mr145099wmk.53.1646843559083; Wed, 09 Mar 2022 08:32:39 -0800 (PST) Received: from localhost ([2a01:4b00:f41a:3600:360b:9754:2e3a:c344]) by smtp.gmail.com with ESMTPSA id p12-20020a5d48cc000000b001e6114938a8sm2053703wrs.56.2022.03.09.08.32.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Mar 2022 08:32:38 -0800 (PST) From: luca.boccassi@gmail.com To: Jiawei Wang Cc: Viacheslav Ovsiienko , Ori Kam , dpdk stable Subject: patch 'net/mlx5: fix NIC egress flow mismatch in switchdev mode' has been queued to stable release 20.11.5 Date: Wed, 9 Mar 2022 16:30:48 +0000 Message-Id: <20220309163053.245754-32-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220309163053.245754-1-luca.boccassi@gmail.com> References: <20220218123931.1749595-1-luca.boccassi@gmail.com> <20220309163053.245754-1-luca.boccassi@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 20.11.5 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 03/11/22. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/bluca/dpdk-stable This queued commit can be viewed at: https://github.com/bluca/dpdk-stable/commit/f400875c4e06f9932276c0c098ee3669bc7a43fb Thanks. Luca Boccassi --- >From f400875c4e06f9932276c0c098ee3669bc7a43fb Mon Sep 17 00:00:00 2001 From: Jiawei Wang Date: Wed, 2 Mar 2022 17:30:51 +0200 Subject: [PATCH] net/mlx5: fix NIC egress flow mismatch in switchdev mode [ upstream commit 6d4f1066be6cd60a95f21ef07a16a3c3676c5cd9 ] When E-Switch mode was enabled, the NIC egress flows was implicitly appended with source vport to match on. If the metadata register C0 was used to maintain the source vport, it was initialized to zero on packet steering engine entry, the flow could be hit only if source vport was zero, the register C0 of the packet was not correct to match in the TX side, this caused egress flow misses. This patch: - removes the implicit source vport match for NIC egress flow. - rejects the NIC egress flows on the representor ports at validation. - allows the internal NIC egress flows containing the TX_QUEUE items in order to not impact hairpins. Fixes: ce777b147bf8 ("net/mlx5: fix E-Switch flow without port item") Signed-off-by: Jiawei Wang Acked-by: Viacheslav Ovsiienko Acked-by: Ori Kam --- doc/guides/nics/mlx5.rst | 2 ++ drivers/net/mlx5/mlx5_flow_dv.c | 26 +++++++++++++++++++++----- 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index b1b9d6f4e3..d76c3178dc 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -352,6 +352,8 @@ Limitations from the reference "Clock Queue" completions, the scheduled send timestamps should not be specified with non-zero MSB. +- The NIC egress flow rules on representor port are not supported. + Statistics ---------- diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 4e87f7a952..44f975c9c9 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -5611,8 +5611,10 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, return ret; last_item = MLX5_FLOW_ITEM_TAG; break; - case MLX5_RTE_FLOW_ITEM_TYPE_TAG: case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE: + last_item = MLX5_FLOW_ITEM_TX_QUEUE; + break; + case MLX5_RTE_FLOW_ITEM_TYPE_TAG: break; case RTE_FLOW_ITEM_TYPE_GTP: ret = flow_dv_validate_item_gtp(dev, items, item_flags, @@ -6273,6 +6275,18 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, NULL, "too many header modify" " actions to support"); } + /* + * Validation the NIC Egress flow on representor, except implicit + * hairpin default egress flow with TX_QUEUE item, other flows not + * work due to metadata regC0 mismatch. + */ + if ((!attr->transfer && attr->egress) && priv->representor && + !(item_flags & MLX5_FLOW_ITEM_TX_QUEUE)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + NULL, + "NIC egress rules on representors" + " is not supported"); return 0; } @@ -10663,12 +10677,14 @@ flow_dv_translate(struct rte_eth_dev *dev, /* * When E-Switch mode is enabled, we have two cases where we need to * set the source port manually. - * The first one, is in case of Nic steering rule, and the second is - * E-Switch rule where no port_id item was found. In both cases - * the source port is set according the current port in use. + * The first one, is in case of NIC ingress steering rule, and the + * second is E-Switch rule where no port_id item was found. + * In both cases the source port is set according the current port + * in use. */ if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) && - (priv->representor || priv->master)) { + (priv->representor || priv->master) && + !(attr->egress && !attr->transfer)) { if (flow_dv_translate_item_port_id(dev, match_mask, match_value, NULL, attr)) return -rte_errno; -- 2.30.2 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2022-03-09 16:30:09.707043643 +0000 +++ 0032-net-mlx5-fix-NIC-egress-flow-mismatch-in-switchdev-m.patch 2022-03-09 16:30:08.599026318 +0000 @@ -1 +1 @@ -From 6d4f1066be6cd60a95f21ef07a16a3c3676c5cd9 Mon Sep 17 00:00:00 2001 +From f400875c4e06f9932276c0c098ee3669bc7a43fb Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit 6d4f1066be6cd60a95f21ef07a16a3c3676c5cd9 ] + @@ -20 +21,0 @@ -Cc: stable@dpdk.org @@ -31 +32 @@ -index c31a154181..2fe5784c04 100644 +index b1b9d6f4e3..d76c3178dc 100644 @@ -34,3 +35,3 @@ -@@ -504,6 +504,8 @@ Limitations - - Matching on checksum and sequence needs OFED 5.6+. +@@ -352,6 +352,8 @@ Limitations + from the reference "Clock Queue" completions, + the scheduled send timestamps should not be specified with non-zero MSB. @@ -40 +40,0 @@ - @@ -42,0 +43 @@ + @@ -44 +45 @@ -index ebd0a427f3..34d2c7a99f 100644 +index 4e87f7a952..44f975c9c9 100644 @@ -47 +48 @@ -@@ -7235,8 +7235,10 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, +@@ -5611,8 +5611,10 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, @@ -59,4 +60,4 @@ -@@ -8069,6 +8071,18 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, - return rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_ACTION, NULL, - "sample before modify action is not supported"); +@@ -6273,6 +6275,18 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, + NULL, "too many header modify" + " actions to support"); + } @@ -78 +79 @@ -@@ -13758,11 +13772,13 @@ flow_dv_translate(struct rte_eth_dev *dev, +@@ -10663,12 +10677,14 @@ flow_dv_translate(struct rte_eth_dev *dev, @@ -90,2 +91,3 @@ -- if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) && priv->sh->esw_mode) { -+ if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) && priv->sh->esw_mode && + if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) && +- (priv->representor || priv->master)) { ++ (priv->representor || priv->master) &&