From: Volodymyr Fialko <vfialko@marvell.com>
To: <dev@dpdk.org>, Ankur Dwivedi <adwivedi@marvell.com>,
Anoob Joseph <anoobj@marvell.com>,
Tejasree Kondoj <ktejasree@marvell.com>,
"Pavan Nikhilesh" <pbhagavatula@marvell.com>,
Shijith Thotton <sthotton@marvell.com>
Cc: <jerinj@marvell.com>, Volodymyr Fialko <vfialko@marvell.com>,
<stable@dpdk.org>
Subject: [PATCH] event/cnxk: fix base pointer for SSO head wait
Date: Fri, 25 Mar 2022 11:59:39 +0100 [thread overview]
Message-ID: <20220325105939.1117634-1-vfialko@marvell.com> (raw)
Function roc_sso_hws_head_wait() expects a base as input pointer, and it
will itself get tag_op from the base. By passing tag_op instead of base
pointer to this function will add SSOW_LF_GWS_TAG register offset twice,
which will lead to accessing wrong register.
Fixes: 1f5b3d55c041 ("event/cnxk: store and reuse workslot status")
Cc: stable@dpdk.org
Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>
---
drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 4 ++--
drivers/crypto/cnxk/cn10k_cryptodev_ops.h | 2 +-
drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 4 ++--
drivers/crypto/cnxk/cn9k_cryptodev_ops.h | 2 +-
drivers/event/cnxk/cn10k_worker.c | 3 +--
drivers/event/cnxk/cn9k_worker.c | 7 +++----
6 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c
index d217bbf383..1b08c67fea 100644
--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c
@@ -265,7 +265,7 @@ cn10k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
}
uint16_t
-cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)
+cn10k_cpt_crypto_adapter_enqueue(uintptr_t base, struct rte_crypto_op *op)
{
union rte_event_crypto_metadata *ec_mdata;
struct cpt_inflight_req *infl_req;
@@ -328,7 +328,7 @@ cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)
}
if (!rsp_info->sched_type)
- roc_sso_hws_head_wait(tag_op);
+ roc_sso_hws_head_wait(base);
lmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id;
roc_lmt_submit_steorl(lmt_arg, qp->lmtline.io_addr);
diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.h b/drivers/crypto/cnxk/cn10k_cryptodev_ops.h
index d7e9f87396..1ad4c16873 100644
--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.h
+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.h
@@ -13,7 +13,7 @@ extern struct rte_cryptodev_ops cn10k_cpt_ops;
void cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev);
__rte_internal
-uint16_t cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op,
+uint16_t cn10k_cpt_crypto_adapter_enqueue(uintptr_t base,
struct rte_crypto_op *op);
__rte_internal
uintptr_t cn10k_cpt_crypto_adapter_dequeue(uintptr_t get_work1);
diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c
index ddba9d5dd0..d3858149c7 100644
--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c
@@ -317,7 +317,7 @@ cn9k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
}
uint16_t
-cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)
+cn9k_cpt_crypto_adapter_enqueue(uintptr_t base, struct rte_crypto_op *op)
{
union rte_event_crypto_metadata *ec_mdata;
struct cpt_inflight_req *infl_req;
@@ -374,7 +374,7 @@ cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)
}
if (!rsp_info->sched_type)
- roc_sso_hws_head_wait(tag_op);
+ roc_sso_hws_head_wait(base);
cn9k_cpt_inst_submit(&inst, qp->lmtline.lmt_base, qp->lmtline.io_addr);
diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.h b/drivers/crypto/cnxk/cn9k_cryptodev_ops.h
index 309f507346..9f6dc24603 100644
--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.h
+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.h
@@ -12,7 +12,7 @@ extern struct rte_cryptodev_ops cn9k_cpt_ops;
void cn9k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev);
__rte_internal
-uint16_t cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op,
+uint16_t cn9k_cpt_crypto_adapter_enqueue(uintptr_t base,
struct rte_crypto_op *op);
__rte_internal
uintptr_t cn9k_cpt_crypto_adapter_dequeue(uintptr_t get_work1);
diff --git a/drivers/event/cnxk/cn10k_worker.c b/drivers/event/cnxk/cn10k_worker.c
index 975a22336a..1ffd48a5ab 100644
--- a/drivers/event/cnxk/cn10k_worker.c
+++ b/drivers/event/cnxk/cn10k_worker.c
@@ -68,6 +68,5 @@ cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)
RTE_SET_USED(nb_events);
- return cn10k_cpt_crypto_adapter_enqueue(ws->base + SSOW_LF_GWS_TAG,
- ev->event_ptr);
+ return cn10k_cpt_crypto_adapter_enqueue(ws->base, ev->event_ptr);
}
diff --git a/drivers/event/cnxk/cn9k_worker.c b/drivers/event/cnxk/cn9k_worker.c
index a981bc986f..fca1f0dffa 100644
--- a/drivers/event/cnxk/cn9k_worker.c
+++ b/drivers/event/cnxk/cn9k_worker.c
@@ -128,8 +128,7 @@ cn9k_sso_hws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)
RTE_SET_USED(nb_events);
- return cn9k_cpt_crypto_adapter_enqueue(ws->base + SSOW_LF_GWS_TAG,
- ev->event_ptr);
+ return cn9k_cpt_crypto_adapter_enqueue(ws->base, ev->event_ptr);
}
uint16_t __rte_hot
@@ -139,6 +138,6 @@ cn9k_sso_hws_dual_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)
RTE_SET_USED(nb_events);
- return cn9k_cpt_crypto_adapter_enqueue(
- dws->base[!dws->vws] + SSOW_LF_GWS_TAG, ev->event_ptr);
+ return cn9k_cpt_crypto_adapter_enqueue(dws->base[!dws->vws],
+ ev->event_ptr);
}
--
2.25.1
next reply other threads:[~2022-03-25 10:59 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-25 10:59 Volodymyr Fialko [this message]
2022-05-13 11:47 ` Jerin Jacob
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