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From: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
To: <dev@dpdk.org>
Cc: <stable@dpdk.org>, Matan Azrad <matan@nvidia.com>,
	Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Subject: [PATCH] common/mlx5: fix MR range calculation
Date: Thu, 31 Mar 2022 17:33:16 +0300	[thread overview]
Message-ID: <20220331143316.3343802-1-dkozlyuk@nvidia.com> (raw)

MR end for a mempool chunk may be calculated incorrectly.
For example, for chunk with addr=1.5M and len=1M with 2M page size
the range would be [0, 2M), while the proper result is [0, 4M).
Fix the calculation.

Fixes: 690b2a88c2f7 ("common/mlx5: add mempool registration facilities")
Cc: stable@dpdk.org

Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/common/mlx5/mlx5_common_mr.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/common/mlx5/mlx5_common_mr.c b/drivers/common/mlx5/mlx5_common_mr.c
index fa27bd98de..06e4c8f187 100644
--- a/drivers/common/mlx5/mlx5_common_mr.c
+++ b/drivers/common/mlx5/mlx5_common_mr.c
@@ -1289,11 +1289,12 @@ mlx5_range_from_mempool_chunk(struct rte_mempool *mp, void *opaque,
 			      unsigned int idx)
 {
 	struct mlx5_range *ranges = opaque, *range = &ranges[idx];
+	uintptr_t start = (uintptr_t)memhdr->addr;
 	uint64_t page_size = rte_mem_page_size();
 
 	RTE_SET_USED(mp);
-	range->start = RTE_ALIGN_FLOOR((uintptr_t)memhdr->addr, page_size);
-	range->end = RTE_ALIGN_CEIL(range->start + memhdr->len, page_size);
+	range->start = RTE_ALIGN_FLOOR(start, page_size);
+	range->end = RTE_ALIGN_CEIL(start + memhdr->len, page_size);
 }
 
 /**
-- 
2.25.1


             reply	other threads:[~2022-03-31 14:33 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-31 14:33 Dmitry Kozlyuk [this message]
2022-04-12  8:08 ` Raslan Darawsheh

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