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Thu, 31 Mar 2022 07:33:21 -0700 From: Dmitry Kozlyuk To: CC: , Matan Azrad , Viacheslav Ovsiienko Subject: [PATCH] common/mlx5: fix MR range calculation Date: Thu, 31 Mar 2022 17:33:16 +0300 Message-ID: <20220331143316.3343802-1-dkozlyuk@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: cc2dc582-ae01-4e9c-6126-08da13236968 X-MS-TrafficTypeDiagnostic: DM6PR12MB5699:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MfsYssnEEdNjIS8KJgZVqOgJ5h8DQNsfPr2+1xyZZY+m/2rs+nhns833JBa9VWnWCQ6J/xhnF7uAdEQ7ZrSdm4xeRMnvT38HRj92o2HCGqKV4a3tDSkrNCuNCphE31l4kfRnP33ARaEnZdj1OziOD2IASrwwjGK16prFFTraMX4OL7Cym2a83M9gYMgRzeBtBBG26jowilz2yP6n/VV0D1u82KfF9jqFEiVggivwY8YRcmFF9Ye0fk2TcaYanxyhaxN7oc2VSnZaMBac+K90rLfC466mO6wbWYNIJOcsmE4BDZ76W5ja6zwlqm0bAukB6SgnYl9AgCjyLB8trpZ3DfArt+Fwjucgp2LIzV/gD2Z9iCKr2sMrsh12kbN89VtZr9Fy9N8bH0/k4ai5YkIoQS2Ur4wvkwidz51TeZVgti0XHAAeDPTUPAptTDoZO7vln9U3/bS6E5+7Mr+VCwqkHj05oJCXfUIAp3W9sBovynOl8ubhlEdabJkSsyPhOLO9atMy4xuo0FLGnaT3fffRYQ+UwnzwhBMwbyNDbPdDe0vNbxASUkzXYmOeliMJbq1CS93FjWbCQ4j4hNRYYs0kmykQeV0RPI+MqKQnVT+F4CHVkCrTHyK1eGYNqTyYfhqdivu/Ix1hMqpmrvgGnDSx3GGld/uQTRhalnm7AE98Pq32JS28TTN02p764KKHqyW6cpNIsXOA39voSG11nCOFog== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(336012)(81166007)(5660300002)(86362001)(426003)(8936002)(82310400004)(36860700001)(47076005)(83380400001)(55016003)(6666004)(1076003)(7696005)(6286002)(8676002)(54906003)(36756003)(70586007)(70206006)(450100002)(508600001)(2616005)(316002)(107886003)(6916009)(2906002)(4326008)(186003)(356005)(26005)(40460700003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Mar 2022 14:33:23.7859 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc2dc582-ae01-4e9c-6126-08da13236968 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT007.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB5699 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org MR end for a mempool chunk may be calculated incorrectly. For example, for chunk with addr=1.5M and len=1M with 2M page size the range would be [0, 2M), while the proper result is [0, 4M). Fix the calculation. Fixes: 690b2a88c2f7 ("common/mlx5: add mempool registration facilities") Cc: stable@dpdk.org Signed-off-by: Dmitry Kozlyuk Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_common_mr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/common/mlx5/mlx5_common_mr.c b/drivers/common/mlx5/mlx5_common_mr.c index fa27bd98de..06e4c8f187 100644 --- a/drivers/common/mlx5/mlx5_common_mr.c +++ b/drivers/common/mlx5/mlx5_common_mr.c @@ -1289,11 +1289,12 @@ mlx5_range_from_mempool_chunk(struct rte_mempool *mp, void *opaque, unsigned int idx) { struct mlx5_range *ranges = opaque, *range = &ranges[idx]; + uintptr_t start = (uintptr_t)memhdr->addr; uint64_t page_size = rte_mem_page_size(); RTE_SET_USED(mp); - range->start = RTE_ALIGN_FLOOR((uintptr_t)memhdr->addr, page_size); - range->end = RTE_ALIGN_CEIL(range->start + memhdr->len, page_size); + range->start = RTE_ALIGN_FLOOR(start, page_size); + range->end = RTE_ALIGN_CEIL(start + memhdr->len, page_size); } /** -- 2.25.1