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Sun, 10 Apr 2022 01:52:23 -0700 From: Michael Baum To: CC: Matan Azrad , Viacheslav Ovsiienko , Christian Ehrhardt Subject: [PATCH 19.11 1/3] net/mlx5: add minimum WQE size for striding RQ Date: Sun, 10 Apr 2022 11:52:15 +0300 Message-ID: <20220410085217.922084-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220410085217.922084-1-michaelba@nvidia.com> References: <20220410085217.922084-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 02101774-3f39-4392-130f-08da1acf6fbe X-MS-TrafficTypeDiagnostic: CY4PR12MB1848:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0NklTqusaW4Lfzvq5S8dz9ivHl8PrVaIwMA4I3qvZqlA4uYNSPjc4+9OoXPGGEu0T7wFp2otmSLZvNcDre7o2g5F6rwSmhM2LNSrtiQmwm7/7PGqv7AYMYpXjznHEUrc8ON7P3phi3S3M+1kurP/ACINGhTRN8DC/RSft9dszF5FUkcqzY+XbP4qBvc0X27c6eVDEe2rt8ffSlLPicpVQQkGljgJAg/5H4soKZbq5pcVjbEGVdiArsrORjIn+V1WNLmIUhOGDoeSpIVukm+eWCrVwV1aoSRWm5j5lxUrTb6WhG5RV01AYwh5hntb1XHq2KTDa0wy4b6V9AVck06Jl5LNEduWzWgos7ONOSNA7lo1QHhn9GNsEgTfVFeBeiDaRhKacfDN4BCdfqaqTkIdAho2Fi1Q1ctlsyTNQzxjEJi+MvjSRwVz3Pst4/Ge0PLvh0oANtp7fVXExrXm6cdPSnnqDZh2rMl8Nn4VfHf1KPo0eK3zawc6KCjqf3I4UjCt2V1wPRzScMYUB1mP8JtdtFbwQtunUwI8pfATEpC6W0Z7uTDsTV4YVQfwpL5IDk/qJlR7sftigVHVQHJSzK0fNOlU7cpN0NNEqcKlaMfTbO1/sWmzO0QCdLBkGs//7eW82rzqH40SQCoS8CO3+wcD6hNImQLZwj4icvudusJKGZcjYKvlXrqJCtzI14lOtP7kcygyWFLOxByWZiGh/03MNA== X-Forefront-Antispam-Report: CIP:12.22.5.235; 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On some newer devices, this limitation is smaller and information on its size is provided by the firmware. This patch adds the attribute query from firmware: the minimum required size of WQE buffer for striding RQ in granularity of Bytes. Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_devx_cmds.c | 28 +++++++++++++++++++++++ drivers/net/mlx5/mlx5_prm.h | 38 ++++++++++++++++++++++++++++++- 3 files changed, 66 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 9f6b355182..1edc28255e 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -193,6 +193,7 @@ struct mlx5_hca_qos_attr { struct mlx5_hca_attr { uint32_t eswitch_manager:1; uint32_t flow_counters_dump:1; + uint32_t log_min_stride_wqe_sz:5; uint8_t flow_counter_bulk_alloc_bitmap; uint32_t eth_net_offloads:1; uint32_t eth_virt:1; diff --git a/drivers/net/mlx5/mlx5_devx_cmds.c b/drivers/net/mlx5/mlx5_devx_cmds.c index f9c4043c11..f6977315d0 100644 --- a/drivers/net/mlx5/mlx5_devx_cmds.c +++ b/drivers/net/mlx5/mlx5_devx_cmds.c @@ -303,6 +303,7 @@ mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx, uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; void *hcattr; int status, syndrome, rc; + bool hca_cap_2_sup; MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); MLX5_SET(query_hca_cap_in, in, op_mod, @@ -322,6 +323,7 @@ mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx, return -1; } hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); + hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); attr->flow_counter_bulk_alloc_bitmap = MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, @@ -341,6 +343,32 @@ mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx, attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, flex_parser_protocols); attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); + if (hca_cap_2_sup) { + memset(in, 0, sizeof(in)); + memset(out, 0, sizeof(out)); + MLX5_SET(query_hca_cap_in, in, opcode, + MLX5_CMD_OP_QUERY_HCA_CAP); + MLX5_SET(query_hca_cap_in, in, op_mod, + MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | + MLX5_HCA_CAP_OPMOD_GET_CUR); + rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), + out, sizeof(out)); + if (rc) + goto error; + status = MLX5_GET(query_hca_cap_out, out, status); + syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); + if (status) { + DRV_LOG(DEBUG, + "Failed to query DevX HCA capabilities 2," + " status %x, syndrome = %x", status, syndrome); + return -1; + } + hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); + attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, + log_min_stride_wqe_sz); + } + if (attr->log_min_stride_wqe_sz == 0) + attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; if (attr->qos.sup) { MLX5_SET(query_hca_cap_in, in, op_mod, MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h index 1d13bbb009..35a78fdf5d 100644 --- a/drivers/net/mlx5/mlx5_prm.h +++ b/drivers/net/mlx5/mlx5_prm.h @@ -252,6 +252,9 @@ /* The maximum log value of segments per RQ WQE. */ #define MLX5_MAX_LOG_RQ_SEGS 5u +/* Log 2 of the default size of a WQE for Multi-Packet RQ. */ +#define MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE 14U + /* The alignment needed for WQ buffer. */ #define MLX5_WQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE) @@ -881,6 +884,7 @@ enum { MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1, MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1, + MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1, }; enum { @@ -918,7 +922,9 @@ enum { #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9) struct mlx5_ifc_cmd_hca_cap_bits { - u8 reserved_at_0[0x30]; + u8 reserved_at_0[0x20]; + u8 hca_cap_2[0x1]; + u8 reserved_at_21[0xf]; u8 vhca_id[0x10]; u8 reserved_at_40[0x40]; u8 log_max_srq_sz[0x8]; @@ -1254,8 +1260,38 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits { u8 reserved_at_200[0x600]; }; +/* + * HCA Capabilities 2 + */ +struct mlx5_ifc_cmd_hca_cap_2_bits { + u8 reserved_at_0[0x80]; /* End of DW4. */ + u8 reserved_at_80[0x3]; + u8 max_num_prog_sample_field[0x5]; + u8 reserved_at_88[0x3]; + u8 log_max_num_reserved_qpn[0x5]; + u8 reserved_at_90[0x3]; + u8 log_reserved_qpn_granularity[0x5]; + u8 reserved_at_98[0x3]; + u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */ + u8 max_reformat_insert_size[0x8]; + u8 max_reformat_insert_offset[0x8]; + u8 max_reformat_remove_size[0x8]; + u8 max_reformat_remove_offset[0x8]; /* End of DW6. */ + u8 reserved_at_c0[0x3]; + u8 log_min_stride_wqe_sz[0x5]; + u8 reserved_at_c8[0x3]; + u8 log_conn_track_granularity[0x5]; + u8 reserved_at_d0[0x3]; + u8 log_conn_track_max_alloc[0x5]; + u8 reserved_at_d8[0x3]; + u8 log_max_conn_track_offload[0x5]; + u8 reserved_at_e0[0x20]; /* End of DW7. */ + u8 reserved_at_100[0x700]; +}; + union mlx5_ifc_hca_cap_union_bits { struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; + struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; struct mlx5_ifc_qos_cap_bits qos_cap; -- 2.25.1