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Mon, 25 Apr 2022 02:30:30 -0700 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , , Subject: [PATCH 2/2] net/mlx5: fix LRO configuration in drop RxQ Date: Mon, 25 Apr 2022 12:30:20 +0300 Message-ID: <20220425093020.125319-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220425093020.125319-1-michaelba@nvidia.com> References: <20220425093020.125319-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a89567de-0409-4036-dd2a-08da269e3f92 X-MS-TrafficTypeDiagnostic: DM4PR12MB5985:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 61PsxNUwltMqoGCS/VS/Org55MBeQjdq83Br9Gi1MK4YSb0ZJKQDSZU9GOqxW35uoZH5O1B8VLY1KsYEGh5lYYIq5Q73V/1bgaXFdo5vzgzEt20feFr8gEThoT1lXsIb9xiaSxu3mzSu/ujqi/+k79YVeyRNThQZBO7O+/9wpC7L20kQ3hnJX9tgApH6GQxeh9eOc1TRWvHrr2pJQCG9ClWQMwPi6V0PXvVgbtLVhvySPHFsHeW/4cCn3mAMnn9BhPqr3ZnsNaiCuXjjyGdXLRSHgoxTXS+YPvmzb1TuVAkug7lcKqoMag/hHACnk2zPkEioxztmIwYcFbrrqZWjxS0MWGE725B2ANnhY39uS5GiVoQIPZvHexTfegizZ0bwk5WdDD3tLTn/dg7Fn/Nocc+gDRkfUwHXNBYQ8hTOK35TG6u9UM+UcNKOfMxIV6bXskb+z1Qg+Tz0o300e7z5wkOVqcTOOTXZr/G9gPNJtyV75qWUgwT93ew7f3yfPh+jhi1DNSd7E3OxtkQi4UFqIvda5jDIy7UvJ/hX+B5n+bpmr6k5e3Imosut1dE7fzpidndFmY3e1K91mDX7Dv5PwywhL4oxIf7JN0iOEAkk51a5pKE3nUWHGTDeezqjAgcn+YDqghizTbR4IyAk82o95lTPQ5C8KtE6y3joD8ynZ9d+PX3vwE/oF9iPegjjRcUJqUBsl9XFBo3RYMXnAAHCMwzAxZ7KcQIRk4iPQurfV5VixPVMi0GUR/V0QrH+NADOfQzMNR0EtDaloRCj3TTJig== X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(426003)(336012)(6666004)(8936002)(36756003)(55016003)(47076005)(4326008)(6286002)(5660300002)(26005)(508600001)(450100002)(82310400005)(36860700001)(8676002)(83380400001)(40460700003)(70206006)(7696005)(54906003)(70586007)(356005)(86362001)(2616005)(6916009)(186003)(316002)(1076003)(2906002)(81166007)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Apr 2022 09:30:33.8530 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a89567de-0409-4036-dd2a-08da269e3f92 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5985 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org The driver wrongly set the LRO configurations to the TIR of the DevX drop queue even when LRO is not supported. Actually, the LRO configuration is not relevant to the drop queue at all. This causes failure in the initialization of the device, which doesn't support LRO where the drop queue is created. Probably, the drop queue creation by DevX missed the fact that LRO is set by default in the TIR creation function and didn't unset it in the drop queue case like other cases that unset LRO. Move the default LRO configuration to unset it and set it only in the case of all the TIR queues configured with LRO. Fixes: bc5bee028ebc ("net/mlx5: create drop queue using DevX") Cc: dkozlyuk@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_devx.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 5ab092a259..03c0fac32f 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -715,7 +715,7 @@ mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key, { struct mlx5_priv *priv = dev->data->dev_private; bool is_hairpin; - bool lro = true; + bool lro = false; uint32_t i; /* NULL queues designate drop queue. */ @@ -724,9 +724,9 @@ mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key, } else if (mlx5_is_external_rxq(dev, ind_tbl->queues[0])) { /* External RxQ supports neither Hairpin nor LRO. */ is_hairpin = false; - lro = false; } else { is_hairpin = mlx5_rxq_is_hairpin(dev, ind_tbl->queues[0]); + lro = true; /* Enable TIR LRO only if all the queues were configured for. */ for (i = 0; i < ind_tbl->queues_n; ++i) { struct mlx5_rxq_data *rxq_i = @@ -776,6 +776,7 @@ mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key, if (dev->data->dev_conf.lpbk_mode) tir_attr->self_lb_block = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; if (lro) { + MLX5_ASSERT(priv->sh->dev_cap.lro_supported); tir_attr->lro_timeout_period_usecs = priv->config.lro_timeout; tir_attr->lro_max_msg_sz = priv->max_lro_msg_size; tir_attr->lro_enable_mask = -- 2.25.1