From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 672A4A00C2 for ; Mon, 2 May 2022 10:47:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5F481410FC; Mon, 2 May 2022 10:47:46 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 203BE40E28; Mon, 2 May 2022 10:47:43 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.16.1.2) with ESMTP id 2420xO32012660; Mon, 2 May 2022 01:47:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=1gigiV4jxNxkmvXx2tSlEGNCDBtzShUdydPsmjagToA=; b=MJYkV0yCeh3MnLYVdMqzElnWAq1VPKYZbijhqUYU0riVPbQp8YsMoadsokDLEj1DiupA wtxGVc4ruIcfMOcn7Y2oI0Sy0kkfHkp3bA/+W7EvuPDoK2xr2N1ICjsawz+3E1LVUqNk MPnEANBTIVQc+baD2veh4uWjZGl2Qpb94GSohum8qqcGz6YddfEzT9gdPDWGVmF81Mi/ iAmhomR3CnPZwcSYs/x5qBQVugGMLySluPj/TZje/khUNTam/ScNtU0k1IiDADrcdAuk WowsbfdqG280QYn+k8Y3pvIHKRsQ+Zv91cK8ENVFJTqlx7Sp+e5Bhf4qA/9cgu3y0XVr sA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fs2fmw6gc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 02 May 2022 01:47:42 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 2 May 2022 01:47:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 2 May 2022 01:47:41 -0700 Received: from localhost.localdomain (unknown [10.28.34.33]) by maili.marvell.com (Postfix) with ESMTP id 32F2A3F703F; Mon, 2 May 2022 01:47:38 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Satheesh Paul , Subject: [dpdk-dev] [PATCH] common/cnxk: fix channel number setting in MCAM entries Date: Mon, 2 May 2022 14:17:30 +0530 Message-ID: <20220502084730.609989-1-psatheesh@marvell.com> X-Mailer: git-send-email 2.25.4 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: MRUcUY3Mep8bGqOBK9pWsL5dG9FOZBMF X-Proofpoint-ORIG-GUID: MRUcUY3Mep8bGqOBK9pWsL5dG9FOZBMF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-02_03,2022-04-28_01,2022-02-23_01 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org From: Satheesh Paul Adding changes to accommodate the following requirements while masking the channel number. 1. For CN10K device, channel number should not be masked for first pass rules with RTE_FLOW_ACTION_TYPE_SECURITY action. And channel number should be masked for all other flow rules. 2. For CN9K device channel number should not be masked. Fixes: 29dcc20985 ("common/cnxk: support for CPT second pass flow rules") Cc: stable@dpdk.org Signed-off-by: Satheesh Paul Reviewed-by: Kiran Kumar Kokkilagadda --- drivers/common/cnxk/roc_npc_mcam.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c index bccbaaa51f..0ae58da0ba 100644 --- a/drivers/common/cnxk/roc_npc_mcam.c +++ b/drivers/common/cnxk/roc_npc_mcam.c @@ -508,19 +508,25 @@ npc_mcam_set_channel(struct roc_npc_flow *flow, req->entry_data.kw_mask[0] &= ~(GENMASK(11, 0)); flow->mcam_data[0] &= ~(GENMASK(11, 0)); flow->mcam_mask[0] &= ~(GENMASK(11, 0)); + chan = channel; + mask = chan_mask; - if (is_second_pass) { - chan = (channel | NIX_CHAN_CPT_CH_START); - mask = (chan_mask | NIX_CHAN_CPT_CH_START); - } else { - /* - * Clear bits 10 & 11 corresponding to CPT - * channel. By default, rules should match - * both first pass packets and second pass - * packets from CPT. - */ - chan = (channel & NIX_CHAN_CPT_X2P_MASK); - mask = (chan_mask & NIX_CHAN_CPT_X2P_MASK); + if (roc_model_runtime_is_cn10k()) { + if (is_second_pass) { + chan = (channel | NIX_CHAN_CPT_CH_START); + mask = (chan_mask | NIX_CHAN_CPT_CH_START); + } else { + if (!(flow->npc_action & NIX_RX_ACTIONOP_UCAST_IPSEC)) { + /* + * Clear bits 10 & 11 corresponding to CPT + * channel. By default, rules should match + * both first pass packets and second pass + * packets from CPT. + */ + chan = (channel & NIX_CHAN_CPT_X2P_MASK); + mask = (chan_mask & NIX_CHAN_CPT_X2P_MASK); + } + } } req->entry_data.kw[0] |= (uint64_t)chan; -- 2.25.4