From: Jiawen Wu <jiawenwu@trustnetic.com>
To: dev@dpdk.org
Cc: Jiawen Wu <jiawenwu@trustnetic.com>, stable@dpdk.org
Subject: [PATCH 4/9] net/ngbe: fix external PHY to power down
Date: Mon, 30 May 2022 17:30:11 +0800 [thread overview]
Message-ID: <20220530093016.16326-5-jiawenwu@trustnetic.com> (raw)
In-Reply-To: <20220530093016.16326-1-jiawenwu@trustnetic.com>
External PHY cannot power down after LAN reset, so need to manually
power down when device stopped.
Fixes: 3d0af7066759 ("net/ngbe: setup PHY link")
Fixes: 1c44384fce76 ("net/ngbe: support custom PHY interfaces")
Cc: stable@dpdk.org
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
drivers/net/ngbe/base/ngbe_dummy.h | 5 +++
drivers/net/ngbe/base/ngbe_phy.c | 2 +
drivers/net/ngbe/base/ngbe_phy_mvl.c | 23 +++++++----
drivers/net/ngbe/base/ngbe_phy_mvl.h | 1 +
drivers/net/ngbe/base/ngbe_phy_yt.c | 59 +++++++++++++---------------
drivers/net/ngbe/base/ngbe_phy_yt.h | 2 +
drivers/net/ngbe/ngbe_ethdev.c | 12 ++----
7 files changed, 57 insertions(+), 47 deletions(-)
diff --git a/drivers/net/ngbe/base/ngbe_dummy.h b/drivers/net/ngbe/base/ngbe_dummy.h
index 836206e325..dd6c2fab96 100644
--- a/drivers/net/ngbe/base/ngbe_dummy.h
+++ b/drivers/net/ngbe/base/ngbe_dummy.h
@@ -237,6 +237,10 @@ static inline s32 ngbe_phy_check_link_dummy(struct ngbe_hw *TUP0, u32 *TUP1,
{
return NGBE_ERR_OPS_DUMMY;
}
+static inline s32 ngbe_phy_set_phy_power_dummy(struct ngbe_hw *TUP0, bool TUP1)
+{
+ return NGBE_ERR_OPS_DUMMY;
+}
static inline s32 ngbe_get_phy_advertised_pause_dummy(struct ngbe_hw *TUP0,
u8 *TUP1)
{
@@ -337,6 +341,7 @@ static inline void ngbe_init_ops_dummy(struct ngbe_hw *hw)
hw->phy.get_lp_adv_pause = ngbe_get_phy_lp_advertised_pause_dummy;
hw->phy.set_pause_adv = ngbe_set_phy_pause_adv_dummy;
hw->phy.led_oem_chk = ngbe_phy_led_oem_chk_dummy;
+ hw->phy.set_phy_power = ngbe_phy_set_phy_power_dummy;
hw->mbx.init_params = ngbe_mbx_init_params_dummy;
hw->mbx.read = ngbe_mbx_read_dummy;
hw->mbx.write = ngbe_mbx_write_dummy;
diff --git a/drivers/net/ngbe/base/ngbe_phy.c b/drivers/net/ngbe/base/ngbe_phy.c
index 1025d7d3a1..84f2925e7e 100644
--- a/drivers/net/ngbe/base/ngbe_phy.c
+++ b/drivers/net/ngbe/base/ngbe_phy.c
@@ -421,6 +421,7 @@ s32 ngbe_init_phy(struct ngbe_hw *hw)
hw->phy.init_hw = ngbe_init_phy_mvl;
hw->phy.check_link = ngbe_check_phy_link_mvl;
hw->phy.setup_link = ngbe_setup_phy_link_mvl;
+ hw->phy.set_phy_power = ngbe_set_phy_power_mvl;
hw->phy.get_adv_pause = ngbe_get_phy_advertised_pause_mvl;
hw->phy.get_lp_adv_pause = ngbe_get_phy_lp_advertised_pause_mvl;
hw->phy.set_pause_adv = ngbe_set_phy_pause_adv_mvl;
@@ -430,6 +431,7 @@ s32 ngbe_init_phy(struct ngbe_hw *hw)
hw->phy.init_hw = ngbe_init_phy_yt;
hw->phy.check_link = ngbe_check_phy_link_yt;
hw->phy.setup_link = ngbe_setup_phy_link_yt;
+ hw->phy.set_phy_power = ngbe_set_phy_power_yt;
hw->phy.get_adv_pause = ngbe_get_phy_advertised_pause_yt;
hw->phy.get_lp_adv_pause = ngbe_get_phy_lp_advertised_pause_yt;
hw->phy.set_pause_adv = ngbe_set_phy_pause_adv_yt;
diff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.c b/drivers/net/ngbe/base/ngbe_phy_mvl.c
index a828597e7b..85af6bc99c 100644
--- a/drivers/net/ngbe/base/ngbe_phy_mvl.c
+++ b/drivers/net/ngbe/base/ngbe_phy_mvl.c
@@ -121,9 +121,7 @@ s32 ngbe_init_phy_mvl(struct ngbe_hw *hw)
value = MVL_INTR_EN_ANC | MVL_INTR_EN_LSC;
hw->phy.write_reg(hw, MVL_INTR_EN, 0, value);
- ngbe_read_phy_reg_mdi(hw, MVL_CTRL, 0, &value);
- value |= MVL_CTRL_PWDN;
- ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
+ hw->phy.set_phy_power(hw, false);
return ret_val;
}
@@ -205,7 +203,7 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,
value_r9 |= value;
hw->phy.write_reg(hw, MVL_PHY_1000BASET, 0, value_r9);
} else {
- hw->phy.autoneg_advertised = 1;
+ hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
hw->phy.read_reg(hw, MVL_ANA, 0, &value);
value &= ~(MVL_PHY_1000BASEX_HALF | MVL_PHY_1000BASEX_FULL);
@@ -217,9 +215,7 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,
ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
skip_an:
- ngbe_read_phy_reg_mdi(hw, MVL_CTRL, 0, &value);
- value |= MVL_CTRL_PWDN;
- ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
+ hw->phy.set_phy_power(hw, true);
hw->phy.read_reg(hw, MVL_INTR, 0, &value);
@@ -356,3 +352,16 @@ s32 ngbe_check_phy_link_mvl(struct ngbe_hw *hw,
return status;
}
+s32 ngbe_set_phy_power_mvl(struct ngbe_hw *hw, bool on)
+{
+ u16 value = 0;
+
+ hw->phy.read_reg(hw, MVL_CTRL, 0, &value);
+ if (on)
+ value &= ~MVL_CTRL_PWDN;
+ else
+ value |= MVL_CTRL_PWDN;
+ hw->phy.write_reg(hw, MVL_CTRL, 0, value);
+
+ return 0;
+}
diff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.h b/drivers/net/ngbe/base/ngbe_phy_mvl.h
index 8aee236390..ab07c99fe4 100644
--- a/drivers/net/ngbe/base/ngbe_phy_mvl.h
+++ b/drivers/net/ngbe/base/ngbe_phy_mvl.h
@@ -97,6 +97,7 @@ s32 ngbe_reset_phy_mvl(struct ngbe_hw *hw);
s32 ngbe_check_phy_link_mvl(struct ngbe_hw *hw,
u32 *speed, bool *link_up);
+s32 ngbe_set_phy_power_mvl(struct ngbe_hw *hw, bool on);
s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw,
u32 speed, bool autoneg_wait_to_complete);
s32 ngbe_get_phy_advertised_pause_mvl(struct ngbe_hw *hw, u8 *pause_bit);
diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c
index 34d69707dd..f46121b8d1 100644
--- a/drivers/net/ngbe/base/ngbe_phy_yt.c
+++ b/drivers/net/ngbe/base/ngbe_phy_yt.c
@@ -100,23 +100,13 @@ s32 ngbe_write_phy_reg_sds_ext_yt(struct ngbe_hw *hw,
s32 ngbe_init_phy_yt(struct ngbe_hw *hw)
{
- u16 value = 0;
-
/* close sds area register */
ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0);
/* enable interrupts */
ngbe_write_phy_reg_mdi(hw, YT_INTR, 0,
YT_INTR_ENA_MASK | YT_SDS_INTR_ENA_MASK);
- /* power down in fiber mode */
- hw->phy.read_reg(hw, YT_BCR, 0, &value);
- value |= YT_BCR_PWDN;
- hw->phy.write_reg(hw, YT_BCR, 0, value);
-
- /* power down in UTP mode */
- ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
- value |= YT_BCR_PWDN;
- ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
+ hw->phy.set_phy_power(hw, false);
return 0;
}
@@ -200,10 +190,7 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN;
hw->phy.write_reg(hw, YT_BCR, 0, value);
skip_an:
- /* power on in UTP mode */
- ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
- value &= ~YT_BCR_PWDN;
- ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
+ hw->phy.set_phy_power(hw, true);
} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) {
/* fiber to rgmii */
hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
@@ -221,19 +208,9 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
/* software reset */
ngbe_write_phy_reg_sds_ext_yt(hw, 0x0, 0, 0x9140);
- /* power on phy */
- hw->phy.read_reg(hw, YT_BCR, 0, &value);
- value &= ~YT_BCR_PWDN;
- hw->phy.write_reg(hw, YT_BCR, 0, value);
+ hw->phy.set_phy_power(hw, true);
} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(2)) {
- /* power on in UTP mode */
- ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
- value &= ~YT_BCR_PWDN;
- ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
- /* power down in fiber mode */
- hw->phy.read_reg(hw, YT_BCR, 0, &value);
- value &= ~YT_BCR_PWDN;
- hw->phy.write_reg(hw, YT_BCR, 0, value);
+ hw->phy.set_phy_power(hw, true);
hw->phy.read_reg(hw, YT_SPST, 0, &value);
if (value & YT_SPST_LINK) {
@@ -303,10 +280,7 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
value &= ~YT_SMI_PHY_SW_RST;
ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value);
- /* power on phy */
- hw->phy.read_reg(hw, YT_BCR, 0, &value);
- value &= ~YT_BCR_PWDN;
- hw->phy.write_reg(hw, YT_BCR, 0, value);
+ hw->phy.set_phy_power(hw, true);
}
ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0);
@@ -434,3 +408,26 @@ s32 ngbe_check_phy_link_yt(struct ngbe_hw *hw,
return status;
}
+s32 ngbe_set_phy_power_yt(struct ngbe_hw *hw, bool on)
+{
+ u16 value = 0;
+
+ /* power down/up in fiber mode */
+ hw->phy.read_reg(hw, YT_BCR, 0, &value);
+ if (on)
+ value &= ~YT_BCR_PWDN;
+ else
+ value |= YT_BCR_PWDN;
+ hw->phy.write_reg(hw, YT_BCR, 0, value);
+
+ value = 0;
+ /* power down/up in UTP mode */
+ ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
+ if (on)
+ value &= ~YT_BCR_PWDN;
+ else
+ value |= YT_BCR_PWDN;
+ ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
+
+ return 0;
+}
diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.h b/drivers/net/ngbe/base/ngbe_phy_yt.h
index dca5174e4e..06e8f77261 100644
--- a/drivers/net/ngbe/base/ngbe_phy_yt.h
+++ b/drivers/net/ngbe/base/ngbe_phy_yt.h
@@ -89,6 +89,8 @@ s32 ngbe_reset_phy_yt(struct ngbe_hw *hw);
s32 ngbe_check_phy_link_yt(struct ngbe_hw *hw,
u32 *speed, bool *link_up);
+s32 ngbe_set_phy_power_yt(struct ngbe_hw *hw, bool on);
+
s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw,
u32 speed, bool autoneg_wait_to_complete);
s32 ngbe_get_phy_advertised_pause_yt(struct ngbe_hw *hw,
diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c
index c7301a9616..9df9f824a1 100644
--- a/drivers/net/ngbe/ngbe_ethdev.c
+++ b/drivers/net/ngbe/ngbe_ethdev.c
@@ -1165,6 +1165,8 @@ ngbe_dev_stop(struct rte_eth_dev *dev)
for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
vfinfo[vf].clear_to_send = false;
+ hw->phy.set_phy_power(hw, false);
+
ngbe_dev_clear_queues(dev);
/* Clear stored conf */
@@ -1874,16 +1876,8 @@ ngbe_dev_link_update_share(struct rte_eth_dev *dev,
return rte_eth_linkstatus_set(dev, &link);
}
- if (!link_up) {
- if (hw->phy.media_type == ngbe_media_type_fiber &&
- hw->phy.type != ngbe_phy_mvl_sfi) {
- intr->flags |= NGBE_FLAG_NEED_LINK_CONFIG;
- rte_eal_alarm_set(10,
- ngbe_dev_setup_link_alarm_handler, dev);
- }
-
+ if (!link_up)
return rte_eth_linkstatus_set(dev, &link);
- }
intr->flags &= ~NGBE_FLAG_NEED_LINK_CONFIG;
link.link_status = RTE_ETH_LINK_UP;
--
2.27.0
next prev parent reply other threads:[~2022-05-30 9:22 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20220530093016.16326-1-jiawenwu@trustnetic.com>
2022-05-30 9:30 ` [PATCH 1/9] net/ngbe: fix to set force speed Jiawen Wu
2022-05-30 9:30 ` [PATCH 3/9] net/ngbe: fix occasional failure of reading PHY ID Jiawen Wu
2022-05-30 9:30 ` Jiawen Wu [this message]
2022-05-30 9:30 ` [PATCH 5/9] net/ngbe: fix to read M88E1512 PHY mode Jiawen Wu
2022-05-30 9:30 ` [PATCH 6/9] net/ngbe: change PCIe related operations to use rte API Jiawen Wu
2022-05-30 9:30 ` [PATCH 7/9] net/ngbe: redesign internal PHY init flow Jiawen Wu
2022-05-30 9:30 ` [PATCH 8/9] net/txgbe: fix SGMII mode to link up Jiawen Wu
2022-05-30 9:30 ` [PATCH 9/9] net/txgbe: fix max number of queues for SRIOV Jiawen Wu
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