[PATCH 20.11] net/bnxt: fix tunnel stateless offloads

[Kalesh A P <kalesh-anakkur.purayil@broadcom.com>]

From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>

[ upstream commit c0278f6e52399f7612f9f1a9d52434071ac49921 ]
[ upstream commit 41dfa14c9c6587dc934042c04ce7f86015acd608 ]

The HW only supports tunnel header parsing globally for supported tunnel
types. When a function uses one default VNIC to receive both the tunnel
and non-tunnel packets, applying the same stateless offload operation to
both tunnel and non-tunnel packets can cause problems in certain scenarios.
To workaround these problems, the firmware advertises no tunnel header
parsing capabilities to the driver using the HWRM_FUNC_QCAPS.
The driver must check this flag setting and accordingly not advertise
tunnel packet stateless offload capabilities to the stack.

If the device supports VXLAN, GRE, IPIP and GENEVE tunnel parsing,
then reports RX_OFFLOAD_OUTER_IPV4_CKSUM, RX_OFFLOAD_OUTER_UDP_CKSUM
and TX_OFFLOAD_OUTER_IPV4_CKSUM in the Rx/Tx offload capabilities of
the device.
Also, advertise tunnel TSO capabilities based on FW support.

Fixes: 0a6d2a720078 ("net/bnxt: get device infos")

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
 drivers/net/bnxt/bnxt.h                |  1 +
 drivers/net/bnxt/bnxt_hwrm.c           |  4 ++
 drivers/net/bnxt/bnxt_hwrm.h           | 20 +++++++++
 drivers/net/bnxt/bnxt_rxq.c            |  7 ++--
 drivers/net/bnxt/bnxt_txq.c            | 19 ++++++---
 drivers/net/bnxt/hsi_struct_def_dpdk.h | 74 +++++++++++++++++++++++++++++++++-
 6 files changed, 114 insertions(+), 11 deletions(-)

diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 0696b8a..4354c0f 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -835,6 +835,7 @@ struct bnxt {
 	uint32_t		max_mcast_addr; /* maximum number of mcast filters supported */
 
 	struct rte_eth_rss_conf	rss_conf; /* RSS configuration. */
+	uint16_t tunnel_disable_flag; /* tunnel stateless offloads status */
 };
 
 static
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index deebea4..44070ca 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -824,6 +824,10 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 		bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
 		PMD_DRV_LOG(DEBUG, "VLAN acceleration for TX is enabled\n");
 	}
+	bp->tunnel_disable_flag = rte_le_to_cpu_16(resp->tunnel_disable_flag);
+	if (bp->tunnel_disable_flag)
+		PMD_DRV_LOG(DEBUG, "Tunnel parsing capability is disabled, flags : %#x\n",
+			    bp->tunnel_disable_flag);
 unlock:
 	HWRM_UNLOCK();
 
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index d36defb..813ac33 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -120,6 +120,26 @@ struct bnxt_pf_resource_info {
 
 #define BNXT_CTX_VAL_INVAL	0xFFFF
 
+#define BNXT_TUNNELED_OFFLOADS_CAP_VXLAN_EN(bp)		\
+	(!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN))
+#define BNXT_TUNNELED_OFFLOADS_CAP_NGE_EN(bp)		\
+	(!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NGE))
+#define BNXT_TUNNELED_OFFLOADS_CAP_GRE_EN(bp)		\
+	(!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_GRE))
+#define BNXT_TUNNELED_OFFLOADS_CAP_IPINIP_EN(bp)	\
+	(!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP))
+
+/*
+ * If the device supports VXLAN, GRE, IPIP and GENEVE tunnel parsing, then report
+ * RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM and
+ * RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM in the Rx/Tx offload capabilities of the device.
+ */
+#define BNXT_TUNNELED_OFFLOADS_CAP_ALL_EN(bp)			\
+	(BNXT_TUNNELED_OFFLOADS_CAP_VXLAN_EN(bp) &&		\
+	 BNXT_TUNNELED_OFFLOADS_CAP_NGE_EN(bp)   &&		\
+	 BNXT_TUNNELED_OFFLOADS_CAP_GRE_EN(bp)   &&		\
+	 BNXT_TUNNELED_OFFLOADS_CAP_IPINIP_EN(bp))
+
 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp,
 				   struct bnxt_vnic_info *vnic);
 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic,
diff --git a/drivers/net/bnxt/bnxt_rxq.c b/drivers/net/bnxt/bnxt_rxq.c
index 7959d48..f597f37 100644
--- a/drivers/net/bnxt/bnxt_rxq.c
+++ b/drivers/net/bnxt/bnxt_rxq.c
@@ -34,14 +34,15 @@ uint64_t bnxt_get_rx_port_offloads(struct bnxt *bp)
 			  DEV_RX_OFFLOAD_SCATTER |
 			  DEV_RX_OFFLOAD_RSS_HASH;
 
-	rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
-			   DEV_RX_OFFLOAD_OUTER_UDP_CKSUM;
-
 	if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 		rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 	if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
 		rx_offload_capa |= DEV_RX_OFFLOAD_VLAN_STRIP;
 
+	if (BNXT_TUNNELED_OFFLOADS_CAP_ALL_EN(bp))
+		rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
+				   DEV_RX_OFFLOAD_OUTER_UDP_CKSUM;
+
 	return rx_offload_capa;
 }
 
diff --git a/drivers/net/bnxt/bnxt_txq.c b/drivers/net/bnxt/bnxt_txq.c
index bc17970..d282d07 100644
--- a/drivers/net/bnxt/bnxt_txq.c
+++ b/drivers/net/bnxt/bnxt_txq.c
@@ -8,6 +8,7 @@
 #include <rte_malloc.h>
 
 #include "bnxt.h"
+#include "bnxt_hwrm.h"
 #include "bnxt_ring.h"
 #include "bnxt_txq.h"
 #include "bnxt_txr.h"
@@ -27,15 +28,21 @@ uint64_t bnxt_get_tx_port_offloads(struct bnxt *bp)
 			  DEV_TX_OFFLOAD_QINQ_INSERT |
 			  DEV_TX_OFFLOAD_MULTI_SEGS;
 
-	tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
-			   DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
-			   DEV_TX_OFFLOAD_GRE_TNL_TSO |
-			   DEV_TX_OFFLOAD_IPIP_TNL_TSO |
-			   DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
-
 	if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
 		tx_offload_capa |= DEV_TX_OFFLOAD_VLAN_INSERT;
 
+	if (BNXT_TUNNELED_OFFLOADS_CAP_ALL_EN(bp))
+		tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
+
+	if (BNXT_TUNNELED_OFFLOADS_CAP_VXLAN_EN(bp))
+		tx_offload_capa |= DEV_TX_OFFLOAD_VXLAN_TNL_TSO;
+	if (BNXT_TUNNELED_OFFLOADS_CAP_GRE_EN(bp))
+		tx_offload_capa |= DEV_TX_OFFLOAD_GRE_TNL_TSO;
+	if (BNXT_TUNNELED_OFFLOADS_CAP_NGE_EN(bp))
+		tx_offload_capa |= DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
+	if (BNXT_TUNNELED_OFFLOADS_CAP_IPINIP_EN(bp))
+		tx_offload_capa |= DEV_TX_OFFLOAD_IPIP_TNL_TSO;
+
 	return tx_offload_capa;
 }
 
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index 81fc68d..f905181 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -10718,7 +10718,7 @@ struct hwrm_func_qcaps_input {
 	uint8_t	unused_0[6];
 } __rte_packed;
 
-/* hwrm_func_qcaps_output (size:704b/88B) */
+/* hwrm_func_qcaps_output (size:768b/96B) */
 struct hwrm_func_qcaps_output {
 	/* The specific error status for the command. */
 	uint16_t	error_code;
@@ -11082,7 +11082,13 @@ struct hwrm_func_qcaps_output {
 	 * (max_tx_rings) to the function.
 	 */
 	uint16_t	max_sp_tx_rings;
-	uint8_t	unused_0[2];
+	/*
+	 * The maximum number of MSI-X vectors that may be allocated across
+	 * all VFs for the function. This is valid only on the PF with SR-IOV
+	 * enabled. Returns zero if this command is called on a PF with
+	 * SR-IOV disabled or on a VF.
+	 */
+	uint16_t	max_msix_vfs;
 	uint32_t	flags_ext;
 	/*
 	 * If 1, the device can be configured to set the ECN bits in the
@@ -11164,6 +11170,70 @@ struct hwrm_func_qcaps_output {
 	 * to the primate processor block.
 	 */
 	#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE     UINT32_C(0x10)
+	/*
+	 * Maximum number of Key Contexts supported per HWRM
+	 * function call for allocating Key Contexts.
+	 */
+	uint16_t	max_key_ctxs_alloc;
+	uint32_t	flags_ext2;
+	/*
+	 * When this bit is '1', it indicates that FW will support
+	 * timestamping on all RX packets, not just PTP type packets.
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED \
+		UINT32_C(0x1)
+	/* When this bit is '1', it indicates that HW and FW support QUIC. */
+	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_QUIC_SUPPORTED \
+		UINT32_C(0x2)
+	uint16_t	tunnel_disable_flag;
+	/*
+	 * When this bit is '1', it indicates that the VXLAN parsing
+	 * is disabled in hardware
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN \
+		UINT32_C(0x1)
+	/*
+	 * When this bit is '1', it indicates that the NGE parsing
+	 * is disabled in hardware
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NGE \
+		UINT32_C(0x2)
+	/*
+	 * When this bit is '1', it indicates that the NVGRE parsing
+	 * is disabled in hardware
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE \
+		UINT32_C(0x4)
+	/*
+	 * When this bit is '1', it indicates that the L2GRE parsing
+	 * is disabled in hardware
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE \
+		UINT32_C(0x8)
+	/*
+	 * When this bit is '1', it indicates that the GRE parsing
+	 * is disabled in hardware
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_GRE \
+		UINT32_C(0x10)
+	/*
+	 * When this bit is '1', it indicates that the IPINIP parsing
+	 * is disabled in hardware
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP \
+		UINT32_C(0x20)
+	/*
+	 * When this bit is '1', it indicates that the MPLS parsing
+	 * is disabled in hardware
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_MPLS \
+		UINT32_C(0x40)
+	/*
+	 * When this bit is '1', it indicates that the PPPOE parsing
+	 * is disabled in hardware
+	 */
+	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE \
+		UINT32_C(0x80)
 	uint8_t	unused_1;
 	/*
 	 * This field is used in Output records to indicate that the output
-- 
2.10.1